Inventor
DEAN E. WALKER
Inventor
US
Overview
Patents· 36 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing63%
H01LSemiconductor devices9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%
G11CStatic stores5%
H04LTransmission of digital information, e.g. telegraphic communication4%
H03KPulse technique2%
PatentTitleYear
12,554,648Evicting a cache line with pending control request202612,530,119Methods and systems for communications between hardware components202612,530,300Memory side cache request handling202612,481,465Host-preferred memory operation202512,367,148Variable execution time atomic operations202512,321,274Recall pending cache line eviction202512,282,800Thread replay to preserve state in a barrel processor202512,190,987Method for configuring multiple input-output channels202512,135,987Thread scheduling control and memory splitting in a barrel processor202412,111,758Synchronized request handling at a memory device202412,111,770Silent cache line eviction202412,079,516Host-preferred memory operation202412,020,064Rescheduling a failed memory request in a processor202412,013,788Evicting a cache line with pending control request202411,960,768Memory-side cache directory-based request queue202411,960,403Variable execution time atomic operations202411,953,989Low-latency register error correction202411,940,919Recall pending cache line eviction202411,914,516Memory side cache request handling202411,868,300Deferred communications over a synchronous interface202411,734,173Memory access bounds checking for a programmable atomic operator202311,722,138Dynamic power and thermal loading in a chiplet-based system202311,698,791On-demand programmable atomic kernel loading202311,669,486Initialization sequencing of chiplet I/O channels within a chiplet system202311,669,487Secondary device detection using a synchronous interface202311,650,876Payload parity protection for a synchronous interface202311,614,942Reuse in-flight register data in a processor202311,586,443Thread-based processor halting202311,507,453Low-latency register error correction202211,488,643Method for configuring multiple input-output channels202211,409,539On-demand programmable atomic kernel loading202211,392,448Payload parity protection for a synchronous interface202211,379,402Secondary device detection using a synchronous interface202211,379,401Deferred communications over a synchronous interface202211,379,365Memory access bounds checking for a programmable atomic operator202211,294,848Initialization sequencing of chiplet I/O channels within a chiplet system2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to MICRON TECHNOLOGY INC (36)· patent assignee history
2022–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 36 | 2022–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 36 | 2022–2026 |