Inventor
Ravishankar Sundaresan
Inventor
Garland, TX, US
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices38%
H10BElectronic memory devices17%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests15%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
B01DSeparation2%
H03KPulse technique2%
PatentTitleYear
RE041670'Sram cell fabrication with interlevel Dielectric planarization'20106,812,142'Method and interlevel dielectric structure for improved metal step coverage'20046,753,576'Method of fabricating a one-sided polysilicon thin film transistor'20046,566,209'Method to form shallow junction transistors while eliminating shorts due to junction spiking'20036,531,750'Shallow junction transistors which eliminating shorts due to junction spiking'20036,297,109'Method to form shallow junction transistors while eliminating shorts due to junction spiking'20016,190,179'Method of making a field effect transistor having a channel in an epitaxial silicon layer'20016,107,642'SRAM cell with thin film transistor using two polysilicon layers'20005,990,528'Thin film transistor with titanium nitride or refractory metal gate in SRAM device serving as source/drain contact electrode of an independent FET'19995,861,643'Self-aligned JFET'19995,723,988'CMOS with parasitic bipolar transistor'19985,721,163'Method of manufacture of thin film transistor SRAM device with a titanium nitride or silicide gate'19985,710,461'SRAM cell fabrication with interlevel dielectric planarization'19985,702,987'Method of manufacture of self-aligned JFET'19975,686,334'Method of making SRAM cell with thin film transistor using two polysilicon layers'19975,554,548'Method of fabricating a one-sided polysilicon thin film transistor'19965,395,785'SRAM cell fabrication with interlevel dielectric planarization'19955,347,152'Stacked CMOS latch with cross-coupled capacitors'19945,346,839'Sidewall doping technique for SOI transistors'19945,304,504'Method of forming a gate overlap LDD structure'19945,298,782'Stacked CMOS SRAM cell with polysilicon transistor load'19945,294,823'SOI BICMOS process'19945,292,670'Sidewall doping technique for SOI transistors'19945,293,053'Elevated CMOS'19945,276,347'Gate overlapping LDD structure'19945,102,809'SOI BICMOS process'19925,072,276'Elevated CMOS'19915,016,070'Stacked CMOS sRAM with vertical transistors and cross-coupled capacitors'19914,956,307'Thin oxide sidewall insulators for silicon-over-insulator transistors'19904,950,618'Masking scheme for silicon dioxide mesa formation'19904,656,731'Method for fabricating stacked CMOS transistors with a self-aligned silicide process'19874,628,589'Method for fabricating stacked CMOS structures'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–1998Patents assigned to TEXAS INSTRUMENTS INC (13)· patent assignee history
1986Based in Dallas, TX, US· patent location history
1987–2004Based in Garland, TX, US· patent location history
1994–1998Patents assigned to SGS THOMSON MICROELECTRONICS (6)· patent assignee history
1997–2003Patents assigned to CHARTERED SEMICONDUCTOR MFG (9)· patent assignee history
1997–2010Based in Plano, TX, US· patent location history
1998Based in Carrollton, TX, US· patent location history
2001–2010Patents assigned to ST MICROELECTRONICS INC (4)· patent assignee history
2001Patents assigned to UNIV SINGAPORE (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 13 | 1986–1998 |
| CHARTERED SEMICONDUCTOR MFG | 9 | 1997–2003 |
| SGS THOMSON MICROELECTRONICS | 6 | 1994–1998 |
| ST MICROELECTRONICS INC | 4 | 2001–2010 |
| UNIV SINGAPORE | 1 | 2001 |
Locations
| Location | Patents | Span |
|---|---|---|
| Garland, Texas, US | 20 | 1987–2004 |
| Plano, Texas, US | 10 | 1997–2010 |
| Carrollton, Texas, US | 1 | 1998 |
| Dallas, Texas, US | 1 | 1986 |