Inventor
Lisa H. Stecker
Inventor
Vancouver, WA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Kprimary
H10KOrganic electric solid-state devices16%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10DInorganic electric semiconductor devices11%
C30BSingle-crystal growth7%
H05KPrinted circuits7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
B41NPrinting plates or foils5%
B82YSpecific uses or applications of nanostructures5%
G11CStatic stores5%
H01LSemiconductor devices5%
PatentTitleYear
9,452,630'Printed ink structure using fluoropolymer template'20169,198,299'Electrohydrodynamic (EHD) printing for the defect repair of contact printed circuits'20159,023,683'Organic semiconductor transistor with epoxy-based organic resin planarization layer'20158,803,139'Bottom and top gate organic transistors with fluropolymer banked crystallization well'20148,765,224'Controlling printed ink line widths using fluoropolymer templates'20148,399,290'Organic transistor with fluropolymer banked crystallization well'20138,367,459'Organic semiconductor interface preparation'20137,727,897'Method of etching a TE/PCMO stack using an etch stop layer'20107,462,499'Carbon nanotube with ZnO asperities'20087,309,621'Method to fabricate a nanowire CHEMFET sensor device using selective nanowire deposition'20077,303,631'Selective growth of ZnO nanostructure using a patterned ALD ZnO seed layer'20077,267,996'Iridium etching for FeRAM applications'20077,199,029'Selective deposition of ZnO nanostructures on a silicon substrate using a nickel catalyst and either patterned polysilicon or silicon surface modification'20077,192,802'ALD ZnO seed layer for deposition of ZnO nanostructures on a silicon substrate'20077,169,637'One mask Pt/PCMO/Pt stack etching process for RRAM applications'20077,098,043'PCMO spin-coat deposition'20067,041,511'Pt/PGO etching process for FeRAM applications'20066,716,691'Self-aligned shallow trench isolation process having improved polysilicon gate thickness control'20046,627,510'Method of making self-aligned shallow trench isolation'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2015Patents assigned to SHARP LAB OF AMERICA INC (18)· patent assignee history
2003–2016Based in Vancouver, WA, US· patent location history
2013–2014Patents assigned to PUNTAMBEKAR KANAN (4)· patent assignee history
2013–2014Patents assigned to ULMER KURT (4)· patent assignee history
2013–2014Patents assigned to STECKER LISA H (3)· patent assignee history
2016Patents assigned to SHARP LABORATORIES AMERICA INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SHARP LAB OF AMERICA INC | 18 | 2003–2015 |
| PUNTAMBEKAR KANAN | 4 | 2013–2014 |
| ULMER KURT | 4 | 2013–2014 |
| STECKER LISA Hself | 3 | 2013–2014 |
| SHARP LABORATORIES AMERICA INC | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Vancouver, Washington, US | 19 | 2003–2016 |