LexDanaLexDanabeta
Inventor

David V. James

Inventor
Palo Alto, CA, US

Overview

83→
Patents
1987–2013
Patent span
Physics
Primary field (CPC G)

Patents· 83 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing38%
H04LTransmission of digital information, e.g. telegraphic communication31%
G11CStatic stores17%
H04JMultiplex communication5%
H04NPictorial communication, e.g. television2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
A61KPreparations for medical, dental or toiletry purposes1%
C07KPeptides1%
G11BInformation storage based on relative movement between record carrier and transducer1%
H03MCoding1%
PatentTitleYear
8,619,567'Method for pacing multi-rate time sensitive traffic on Ethernet and bridge connected networks'20138,543,771'Method for maintaining cache coherence using a distributed directory with event driven updates'20138,195,890'Method for maintaining cache coherence using a distributed directory with event driven updates'20128,073,005'Method and apparatus for configuring signal lines according to idle codes'20117,881,194'Method for pacing multi-rate time sensitive traffic on ethernet and bridge connected networks'20117,474,586'Random access memory (RAM) method of operation and device for search engine systems'20097,401,180'Content addressable memory (CAM) device having selectable access and method therefor'20087,379,352'Random access memory (RAM) method of operation and device for search engine systems'20087,321,592'Method of and apparatus for implementing and sending an asynchronous control mechanism packet used to control bridge devices within a network of IEEE Std 1394 serial buses'20087,301,961'Method and apparatus for configuring signal lines according to idle codes'20077,283,565'Method and apparatus for framing a data packet'20077,185,141'Apparatus and method for associating information values with portions of a content addressable memory (CAM) device'20077,117,300'Method and apparatus for restricted search operation in content addressable memory (CAM) devices'20067,117,301'Packet based communication for content addressable memory (CAM) devices and systems'20067,085,480'AV/C commands for accessing a hard disk device'20067,073,018'Device identification method for systems having multiple device branches'20066,993,022'Method of and apparatus for directly mapping communications through a router between nodes on different buses within a network of buses'20066,954,823'Search engine device and method for generating output search responses from multiple input search responses'20056,928,646'System and method for efficiently performing scheduling operations in an electronic device'20056,910,090'Maintaining communications in a bus bridge interconnect'20056,906,936'Data preclassifier method and apparatus for content addressable memory (CAM) device'20056,903,951'Content addressable memory (CAM) device decoder circuit'20056,898,201'Apparatus and method for inter-node communication'20056,892,273'Method and apparatus for storing mask values in a content addressable memory (CAM) device'20056,879,523'Random access memory (RAM) method of operation and device for search engine systems'20056,876,558'Method and apparatus for identifying content addressable memory device results for multiple requesting sources'20056,847,650'System and method for utilizing a memory device to support isochronous processes'20056,845,024'Result compare circuit and method for content addressable memory (CAM) device'20056,810,452'Method and system for quarantine during bus topology configuration'20046,778,552'Method and system for partitioning an extended network of 1394b devices into subclusters of fully capable and partially capable nodes'20046,763,426'Cascadable content addressable memory (CAM) device and architecture'20046,751,697'Method and system for a multi-phase net refresh on a bus bridge interconnect'2004RE038514'System for and method of efficiently controlling memory accesses in a multiprocessor computer system'20046,728,821'Method and system for adjusting isochronous bandwidths on a bus'20046,690,309'High speed transmission system with clock inclusive balanced coding'20046,684,315'Method and system for supporting multiprocessor TLB-purge instructions using directed write transactions'20046,647,446'Method and system for using a new bus identifier resulting from a bus topology change'20036,633,943'Method and system for the simplification of leaf-limited bridges'20036,631,415'Method and system for providing a communication connection using stream identifiers'20036,584,550'System and method for updating a head entry from read-only to read-write and allowing a list to expand in a cache-coherence sharing list'20036,584,539'Method and system for message broadcast flow control on a bus bridge interconnect'20036,567,896'System and method for deleting read-only head entries in multi-processor computer systems supporting cache coherence with mixed protocols'20036,557,067'System and method to effectively compensate for delays in an electronic interconnect'20036,539,450'Method and system for adjusting isochronous bandwidths on a bus'20036,523,108'Method of and apparatus for extracting a string of bits from a binary bit string and depositing a string of bits onto a binary bit string'20036,519,657'Method and device for identifying an active 1394A node attached to a 1394B network'20036,502,158'Method and system for address spaces'20026,496,907'System and method for updating from a read-only to a read-write entry and concurrently invalidating stale cache copies from head-to-tail and tail-to-head directions'20026,445,711'Method of and apparatus for implementing and sending an asynchronous control mechanism packet used to control bridge devices within a network of IEEE STD 1394 serial buses'20026,442,644'Memory system having synchronous-link DRAM (SLDRAM) devices and controller'20026,421,745'Asynchronous connections with scattering page tables for transmitting data from a producer device to a consumer device over an IEEE 1394 serial data bus'20026,414,971'System and method for delivering data packets in an electronic interconnect'20026,389,547'Method and apparatus to synchronize a bus bridge to a master clock'20026,374,316'Method and system for circumscribing a topology to form ring structures'20026,345,352'Method and system for supporting multiprocessor TLB-purge instructions using directed write transactions'20026,321,304'System and method for deleting read-only head entries in multi-processor computer systems supporting cache coherence with mixed protocols'20016,286,067'Method and system for the simplification of leaf-limited bridges'20016,249,827'Method for transferring data associated with a read/write command between a processor and a reader circuit using a plurality of clock lines'20016,226,723'Bifurcated data and command/address communication bus architecture for random access memories employing synchronous communication protocols'20016,208,645'Time multiplexing of cyclic redundancy functions in point-to-point ringlet-based computer systems'20016,133,938'Descriptor mechanism for assuring indivisible execution of AV/C operations'20006,108,739'Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system'20006,035,376'System and method for changing the states of directory-based caches and memories from read/write to read-only'20006,006,289'System for transferring data specified in a transaction request as a plurality of move transactions responsive to receipt of a target availability signal'19995,961,623'Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system'19995,898,876'Efficient arbitration within point-to-point ringlet-based computer systems'19995,895,496'System for an method of efficiently controlling memory accesses in a multiprocessor computer system'19995,860,080'Multicasting system for selecting a group of memory devices for operation'19995,845,145'System for generating and sending a critical-world-first data response packet by creating response packet having data ordered in the order best matching the desired order'19985,841,989'System and method for efficiently routing data packets in a computer interconnect'19985,835,742'System and method for executing indivisible memory operations in multiple processor computer systems with multiple busses'19985,829,035'System and method for preventing stale data in multiple processor computer systems'19985,815,695'Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor'19985,717,952'DMA controller with mechanism for conditional action under control of status register, prespecified parameters, and condition field of channel command'19985,574,922'Processor with sequences of processor instructions for locked memory updates'19965,495,592'System for finding and setting address portion of variable-length character string by XOR-ing portion in number of bytes within single instruction'19965,323,426'Elasticity buffer for data/clock synchronization'19945,052,029'Self-correcting synchronization signal method and apparatus'19915,008,904'Synchronizer using clock phase extrapolation'19914,779,195'Interrupt system using masking register in processor for selectively establishing device eligibility to interrupt a particular processor'19884,777,589'Direct input/output in a virtual memory system'19884,774,653'Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers'19884,703,418'Method and apparatus for performing variable length data read transactions'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–1991Patents assigned to HEWLETT PACKARD CO (5)· patent assignee history
1987–2013Based in Palo Alto, CA, US· patent location history
1991–2005Patents assigned to APPLE COMPUTER (26)· patent assignee history
2000–2008Patents assigned to SONY ELECTRONICS INC (26)· patent assignee history
2000–2008Patents assigned to SONY CORP (22)· patent assignee history
2004–2011Patents assigned to CYPRESS SEMICONDUCTOR CORP (12)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
APPLE COMPUTER261991–2005
SONY ELECTRONICS INC262000–2008
SONY CORP222000–2008
CYPRESS SEMICONDUCTOR CORP122004–2011
HEWLETT PACKARD CO51987–1991
Locations
LocationPatentsSpan
Palo Alto, California, US831987–2013