Inventor
Harold W. Cain, III
Inventor
Raleigh, NC, US
Overview
Patents· 104 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing94%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
G11CStatic stores1%
H05KPrinted circuits1%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
10,963,387Methods of cache preloading on a partition or a context switch202110,885,015Database system transaction management202110,831,254Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements202010,831,537Dynamic update of the number of architected registers assigned to software threads using spill counts202010,802,971Cache memory transaction shielding via prefetch suppression202010,740,106Determining if transactions that are about to run out of resources can be salvaged or need to be aborted202010,565,003Hint instruction for managing transactional aborts in transactional memory computing environments202010,521,262Memory access request for a memory protocol201910,353,734Prioritization of transactions based on execution by transactional core with super core indicator201910,268,588Methods of cache preloading on a partition or a context switch201910,255,074Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt201910,223,154Hint instruction for managing transactional aborts in transactional memory computing environments201910,223,278Selective bypassing of allocation in a cache201910,210,019Hint instruction for managing transactional aborts in transactional memory computing environments201910,185,668Cost-aware cache replacement201910,169,240Reducing memory access bandwidth based on prediction of memory request size201910,120,803Transactional memory coherence control201810,120,802Transactional memory coherence control201810,102,375Multi-modal memory hierarchical management for mitigating side-channel attacks in the cloud201810,083,076Salvaging lock elision transactions with instructions to change execution type20189,971,626Coherence protocol augmentation to indicate transaction status20189,971,628Salvaging hardware transactions20189,952,943Salvaging hardware transactions20189,928,158'Redundant transactions for detection of timing sensitive errors'20189,870,384'Database system transaction management'20189,846,593Predicting the length of a transaction20179,817,693'Coherence protocol augmentation to indicate transaction status'20179,804,967'Methods of cache preloading on a partition or a context switch'20179,772,874'Prioritization of transactions based on execution by transactional core with super core indicator'20179,772,786'Address probing for transaction'20179,766,829'Address probing for transaction'20179,766,937'Thread-based cache content saving for task switching'20179,760,133'Locking power supplies'20179,753,764'Alerting hardware transactions that are about to run out of space'20179,740,616'Multi-granular cache management in multi-processor computing environments'20179,710,271'Collecting transactional execution characteristics during transactional execution'20179,703,560'Collecting transactional execution characteristics during transactional execution'20179,696,927'Memory transaction having implicit ordering effects'20179,696,928'Memory transaction having implicit ordering effects'20179,697,126'Generating approximate usage measurements for shared cache memory systems'20179,697,128'Prefetch threshold for cache restoration'20179,678,875'Providing shared cache memory allocation control in shared cache memory systems'20179,626,256'Determining failure context in hardware transactional memories'20179,626,187'Transactional memory system supporting unbroken suspended execution'20179,619,383'Dynamic predictor for coalescing memory transactions'20179,619,356'Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor'20179,619,345'Apparatus for determining failure context in hardware transactional memories'20179,547,595'Salvaging lock elision transactions'20179,535,608'Memory access request for a memory protocol'20179,529,723'Methods of cache preloading on a partition or a context switch'20169,507,628'Memory access request for a memory protocol'20169,459,979'Detection of hardware errors using redundant transactions for system test'20169,454,483'Salvaging lock elision transactions with instructions to change execution type'20169,448,835'Thread-based cache content saving for task switching'20169,448,836'Alerting hardware transactions that are about to run out of space'20169,442,776'Salvaging hardware transactions with instructions to transfer transaction execution control'20169,442,775'Salvaging hardware transactions with instructions to transfer transaction execution control'20169,442,853'Salvaging lock elision transactions with instructions to change execution type'20169,436,501'Thread-based cache content saving for task switching'20169,430,273'Suppressing aborting a transaction beyond a threshold execution duration based on the predicted duration'20169,424,072'Alerting hardware transactions that are about to run out of space'20169,411,729'Salvaging lock elision transactions'20169,389,802'Hint instruction for managing transactional aborts in transactional memory computing environments'20169,361,041'Hint instruction for managing transactional aborts in transactional memory computing environments'20169,342,397'Salvaging hardware transactions with instructions'20169,336,097'Salvaging hardware transactions'20169,329,946'Salvaging hardware transactions'20169,329,890'Managing high-coherence-miss cache lines in multi-processor computing environments'20169,311,178'Salvaging hardware transactions with instructions'20169,304,863'Transactions for checkpointing and reverse execution'20169,298,623'Identifying high-conflict cache lines in transactional memory computing environments'20169,298,626'Managing high-conflict cache lines in transactional memory computing environments'20169,292,444'Multi-granular cache management in multi-processor computing environments'20169,268,598'Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories'20169,268,599'Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories'20169,262,207'Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments'20169,262,206'Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments'20169,251,014'Redundant transactions for detection of timing sensitive errors'20169,244,782'Salvaging hardware transactions'20169,244,781'Salvaging hardware transactions'20169,158,573'Dynamic predictor for coalescing memory transactions'20159,092,341'Methods of cache preloading on a partition or a context switch'20159,086,974'Centralized management of high-contention cache lines in multi-processor computing environments'20159,086,986'Detection of conflicts between transactions and page shootdowns'20159,086,987'Detection of conflicts between transactions and page shootdowns'20159,081,607'Conditional transaction abort and precise abort handling'20159,058,270'False sharing detection logic for performance monitoring'20158,972,704'Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory'20158,683,127'Checkpointed tag prefetcher'20148,656,112'Checkpointed tag prefetcher'20148,572,341'Overflow handling of speculative store buffers'20138,544,022'Transactional memory preemption mechanism'20138,539,486'Transactional block conflict resolution based on the determination of executing threads in parallel or in serial mode'20138,424,015'Transactional memory preemption mechanism'20138,392,694'System and method for software initiated checkpoint operations'20138,341,352'Checkpointed tag prefetcher'20128,255,626'Atomic commit predicated on consistency of watches'20128,131,894'Method and system for a sharing buffer'20128,122,438'Computer implemented method and system for accurate, efficient and adaptive calling context profiling'20127,971,039'Conditional memory ordering'20117,921,260'Preferred write-mostly data cache replacement policies'20117,818,722'Computer implemented method and system for accurate, efficient and adaptive calling context profiling'20107,793,049'Mechanism for data cache replacement based on region policies'20107,516,309'Method and apparatus for conditional memory ordering'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2021Patents assigned to IBM (93)· patent assignee history
2009–2017Based in Hartsdale, NY, US· patent location history
2012–2018Patents assigned to CAIN III HAROLD WADE (9)· patent assignee history
2012–2017Patents assigned to CAIN III HAROLD W (8)· patent assignee history
2013–2017Patents assigned to FREY BRADLY G (5)· patent assignee history
2013Based in Yorktown Heights, NY, US· patent location history
2015–2021Based in Raleigh, NC, US· patent location history
2015–2021Based in Katonah, NY, US· patent location history
2017–2020Patents assigned to QUALCOMM INC (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 93 | 2009–2021 |
| CAIN III HAROLD WADEself | 9 | 2012–2018 |
| CAIN III HAROLD Wself | 8 | 2012–2017 |
| QUALCOMM INC | 8 | 2017–2020 |
| FREY BRADLY G | 5 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Raleigh, NC, US | 62 | 2015–2021 |
| Katonah, New York, US | 24 | 2015–2021 |
| Hartsdale, New York, US | 16 | 2009–2017 |
| Yorktown Heights, New York, US | 2 | 2013 |