Inventor
Mark S. Papamarcos
Inventor
San Jose, CA, US
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G01Rprimary
G01RMeasuring electric variables33%
G06FElectric digital data processing33%
H01RElectrically-conductive connections17%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests17%
PatentTitleYear
6,148,275'System for and method of connecting a hardware modeling element to a hardware modeling system'20006,141,636'Logic analysis subsystem in a time-sliced emulator'20005,963,736'Software reconfigurable target I/O in a circuit emulation system'19995,625,580'Hardware modeling system and method of use'19975,369,593'System for and method of connecting a hardware modeling element to a hardware modeling system'19945,353,243'Hardware modeling system and method of use'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2000Patents assigned to SYNOPSYS INC (4)· patent assignee history
1994–2000Based in San Jose, CA, US· patent location history
1999–2000Patents assigned to QUICKTURN DESIGN SYSTEMS INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SYNOPSYS INC | 4 | 1994–2000 |
| QUICKTURN DESIGN SYSTEMS INC | 2 | 1999–2000 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 6 | 1994–2000 |