LexDanaLexDanabeta
Inventor

John W. Poulton

Inventor
Chapel Hill, NC, US

Overview

117→
Patents
1988–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 117 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication17%
G06FElectric digital data processing14%
G11CStatic stores13%
H03KPulse technique9%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%
H03FAmplifiers4%
H04BTransmission4%
PatentTitleYear
11,133,794Signal calibration circuit202111,121,893Equalizing transmitter and method of operation202111,075,671Configurable, power supply voltage referenced single-ended signaling with ESD protection202110,901,485Clock-forwarding memory controller with mesochronously-clocked signaling interface202110,839,863Forwarding signal supply voltage in data transmission system202010,656,851Maintenance operations in a DRAM202010,644,686Self-clocking sampler with reduced metastability202010,601,409Self-clocking sampler with reduced metastability202010,601,324Switched tank-transformer based high step-down ratio DC-DC converter202010,566,958Clock distribution schemes utilizing injection locked oscillation202010,522,194Forwarding signal supply voltage in data transmission system201910,516,442Configurable, power supply voltage referenced single-ended signaling with ESD protection201910,505,769Equalizing transmitter and method of operation201910,331,193Signaling interface with phase and framing calibration201910,298,422Multi-path peaking technique for equalization and supply noise compensation201910,248,342Maintenance operations in a DRAM201910,205,614High-speed signaling systems with adaptable pre-emphasis and equalization201910,200,220Equalizing transmitter and method of operation201910,168,933Maintenance operations in a DRAM201910,164,638Balanced charge-recycling repeater link201810,102,885Forwarding signal supply voltage in data transmission system201810,003,484High-speed signaling systems with adaptable pre-emphasis and equalization20189,954,527Balanced charge-recycling repeater link20189,935,584Self-biased gyrator-based receiver for amplification and equalization of single-ended signals20189,933,960Maintenance operations in a DRAM20189,923,602'Configurable, power supply voltage referenced single-ended signaling with ESD protection'20189,881,652'Forwarding signal supply voltage in data transmission system'20189,753,521'Chip-to-chip signaling link timing calibration'20179,749,160'Equalizing transmitter and method of operation'20179,742,602'High-speed signaling systems with adaptable pre-emphasis and equalization'20179,627,021'8-transistor dual-ported static random access memory'20179,565,039'Forwarding signal supply voltage in data transmission system'20179,553,745'High-speed signaling systems with adaptable pre-emphasis and equalization'20179,437,276'Maintenance operations in a DRAM'20169,418,714'Sense amplifier with transistor threshold compensation'20169,411,668'Approach to predictive verification of write integrity in a memory driver'20169,350,421'Configurable, power supply voltage referenced single-ended signaling with ESD protection'20169,343,449'Alternative 3D stacking scheme for DRAMs atop GPUs'20169,338,036'Data-driven charge-pump transmitter for differential signaling'20169,318,183'Maintenance operations in a DRAM'20169,251,870'Ground-referenced single-ended memory interconnect'20169,245,601'High-density latch arrays'20169,229,523'Memory controller with transaction-queue-dependent power modes'20169,196,348'Maintenance operations in a DRAM'20159,171,607'Ground-referenced single-ended system-on-package'20159,170,980'Ground-referenced single-ended signaling connected graphics processing unit multi-chip module'20159,153,539'Ground-referenced single-ended signaling connected graphics processing unit multi-chip module'20159,148,322'High-speed signaling systems with adaptable pre-emphasis and equalization'20159,147,447'Ground-referenced single-ended memory interconnect'20159,148,313'Equalizing transmitter and method of operation'20159,137,063'High-speed signaling systems with adaptable pre-emphasis and equalization'20159,100,094'System and method for tuning a serial link'20159,094,238'High-speed signaling systems with adaptable pre-emphasis and equalization'20159,076,551'Multi-phase ground-referenced single-ended signaling'20159,071,244'Ground referenced single-ended signaling'20159,043,633'Memory controller with transaction-queue-monitoring power mode circuitry'20158,989,249'High-speed signaling systems with adaptable pre-emphasis and equalization'20158,949,520'Maintenance operations in a DRAM'20158,942,297'Forwarding signal supply voltage in data transmission system'20158,941,430'Timing calibration for on-chip interconnect'20158,935,559'System and method for reducing crosstalk in on-chip networks using a contraflow interconnect and offset repeaters'20158,918,667'Mesochronous signaling system with core-clock synchronization'20148,918,669'Mesochronous signaling system with clock-stopped low power mode'20148,854,123'On-package multiprocessor ground-referenced single-ended interconnect'20148,737,162'Clock-forwarding low-power signaling system'20148,689,159'Redundancy for on-chip interconnect'20148,674,768'Signaling system with low-power automatic gain control'20148,649,475'Partial-rate transfer mode for fixed-clock-rate interface'20148,633,733'Voltage mode transmitter equalizer'20148,611,437'Ground referenced single-ended signaling'20138,605,397'Configurable, power supply voltage referenced single-ended signaling with ESD protection'20138,604,855'Dual-trigger low-energy flip-flop circuit'20138,559,248'Clamped bit line read circuit'20138,513,976'Single-ended signaling with parallel transmit and return current flow'20138,509,094'Edge-based loss-of-signal detection'20138,487,681'Dual-trigger low-energy flip-flop circuit'20138,432,768'Mesochronous signaling system with multiple power modes'20138,363,368'Power supply shunt'20138,339,895'Signal calibration methods and apparatuses'20128,310,294'Low-power clock generation and distribution circuitry'20128,208,593'Partial-rate transfer mode for fixed-clock-rate interface'20128,199,866'Edge-based sampler offset correction'20128,111,093'Power supply noise rejection in PLL or DLL circuits'20128,102,212'Signaling system with low-power automatic gain control'20128,068,357'Memory controller with multi-modal reference pad'20118,064,175'Power supply shunt'20117,812,653'Power supply noise rejection in PLL or DLL circuits'20107,802,212'Processor controlled interface'20107,786,816'Phase controlled oscillator circuit with input signal coupler'20107,782,138'Signaling system with low-power automatic gain control'20107,683,680'Combined phase comparator and charge pump circuit'20107,501,867'Power supply noise rejection in PLL or DLL circuits'20097,498,882'Signaling system with low-power automatic gain control'20097,495,513'Signaling system with low-power automatic gain control'20097,460,565'Data communications circuit with multi-stage multiplexing'20087,414,489'Phase controlled oscillator circuit with input signal coupler'20087,319,345'Wide-range multi-phase clock generator'20087,268,706'Low power, DC-balanced serial link transmitter'20077,199,728'Communication system with low power, DC-balanced serial link'20077,187,721'Transition-time control in a high-speed data transmitter'20077,135,925'Adaptive bias scheme for high-voltage compliance in serial links'20067,088,270'Low power, DC-balanced serial link'20067,078,979'Phase controlled oscillator circuit with input signal coupler'20067,061,406'Low power, DC-balanced serial link transmitter'20066,952,431'Clock multiplying delay-locked loop for data communications'20056,937,073'Frequency multiplier with phase comparator'20056,861,916'Phase controlled oscillator circuit with input signal coupler'20056,807,186'Architectures for a single-stage grooming switch'20046,674,772'Data communications circuit with multi-stage multiplexing'20046,617,936'Phase controlled oscillator'20036,556,628'Methods and systems for transmitting and receiving differential signals over a plurality of conductors'20036,476,656'Low-power low-jitter variable delay timing circuit'20026,316,987'Low-power low-jitter variable delay timing circuit'20016,275,072'Combined phase comparator and charge pump circuit'20015,481,669'Architecture and apparatus for image generation utilizing enhanced memory devices'19965,388,206'Architecture and apparatus for image generation'19954,783,649'VLSI graphics display image buffer using logic enhanced pixel memory cells'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988Based in Durham, NC, US· patent location history
1995–2021Based in Chapel Hill, NC, US· patent location history
2005–2021Patents assigned to RAMBUS INC (75)· patent assignee history
2011–2017Patents assigned to POULTON JOHN W (28)· patent assignee history
2012–2015Patents assigned to WARE FREDERICK A (9)· patent assignee history
2012–2015Patents assigned to PALMER ROBERT E (8)· patent assignee history
2013–2021Patents assigned to NVIDIA CORP (31)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
RAMBUS INC752005–2021
NVIDIA CORP312013–2021
POULTON JOHN Wself282011–2017
WARE FREDERICK A92012–2015
PALMER ROBERT E82012–2015
Locations
LocationPatentsSpan
Chapel Hill, NC, US1161995–2021
Durham, NC, US11988