Inventor
Joseph P. Ellul
Inventor
Nepean, CA
Overview
Patents· 30 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H01LSemiconductor devices8%
C23CCoating metallic material6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
G02BOptical elements, systems or apparatus3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H01FMagnets3%
H01JElectric discharge tubes or discharge lamps3%
PatentTitleYear
10,475,559Controlling the morphology in metal loaded paste material20199,608,130'Semiconductor device having trench capacitor structure integrated therein'20179,520,462'Semiconductor device having capacitor integrated therein'20169,196,672'Semiconductor device having capacitor integrated therein'20159,023,422'High rate deposition method of magnetic nanocomposites'20158,847,365'Inductors and methods for integrated circuits'20148,686,543'3D chip package with shielded structures'20148,344,478'Inductors having inductor axis parallel to substrate surface'20137,943,473'Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme'20116,475,873'Method of forming laser trimmable thin-film resistors in a fully planarized integrated circuit technology'20026,358,809'Method of modifying properties of deposited thin film material'20026,114,227'Chamber for reducing contamination during chemical vapor deposition'20006,079,353'Chamber for reducing contamination during chemical vapor deposition'20005,773,871'Integrated circuit structure and method of fabrication thereof'19985,726,084'Method for forming integrated circuit structure'19985,614,750'Buried layer contact for an integrated circuit structure'19975,516,710'Method of forming a transistor'19965,394,000'Trench capacitor structure'19955,362,669'Method of making integrated circuits'19945,352,923'Trench resistors for integrated circuits'19945,316,978'Forming resistors for intergrated circuits'19945,296,258'Method of forming silicon carbide'19945,275,974'Method of forming electrodes for trench capacitors'19945,035,916'Optical waveguide and method for its manufacture'19914,996,081'Method of forming multiple nitride coating on silicon'19914,968,641'Method for formation of an isolating oxide layer'19904,934,774'Optical waveguide and method for its manufacture'19904,859,303'Method and apparatus for removing coating from substrate'19894,836,902'Method and apparatus for removing coating from substrate'19894,580,155'Deep depletion CCD imager'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–1998Patents assigned to NORTHERN TELECOM LTD (15)· patent assignee history
1986–1998Based in Nepean, CA· patent location history
1990–2014Patents assigned to ELLUL JOSEPH P (4)· patent assignee history
2000–2019Based in San Jose, CA, US· patent location history
2002–2019Patents assigned to MAXIM INTEGRATED PRODUCTS (11)· patent assignee history
2013–2014Patents assigned to BERGEMONT ALBERT (3)· patent assignee history
2013–2014Patents assigned to GODSHALK EDWARD MARTIN (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NORTHERN TELECOM LTD | 15 | 1986–1998 |
| MAXIM INTEGRATED PRODUCTS | 11 | 2002–2019 |
| ELLUL JOSEPH Pself | 4 | 1990–2014 |
| BERGEMONT ALBERT | 3 | 2013–2014 |
| GODSHALK EDWARD MARTIN | 2 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Nepean, CA | 17 | 1986–1998 |
| San Jose, California, US | 13 | 2000–2019 |