LexDanaLexDanabeta
Inventor

David T. Wang

Inventor
San Jose, CA, US

Overview

90→
Patents
1988–2020
Patent span
Physics
Primary field (CPC G)

Patents· 90 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores44%
G06FElectric digital data processing32%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
H03MCoding2%
G01RMeasuring electric variables1%
H05KPrinted circuits1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
PatentTitleYear
10,607,669Memory buffer with data scrambling and error correction202010,606,483Buffering device with status communication method for memory controller202010,198,187Buffering device with status communication method for memory controller201910,185,499Near-memory compute module201910,013,371Configurable memory circuit system and method20189,972,369Memory buffer with data scrambling and error correction20189,727,458'Translating an address associated with a command communicated between a system and memory circuits'20179,632,929'Translating an address associated with a command communicated between a system and memory circuits'20179,542,352'System and method for reducing command scheduling constraints of memory circuits'20179,542,353'System and method for reducing command scheduling constraints of memory circuits'20179,507,739'Configurable memory circuit system and method'20169,348,539'Memory centric computing'20169,349,433'Hidden refresh of weak memory storage cells in semiconductor memory'20169,317,366'Protocol checking logic circuit for memory system reliability'20169,250,831'Isolated shared memory architecture (iSMA)'20169,239,355'Memory test sequencer'20169,240,248'Method of using non-volatile memories for on-DIMM memory address list storage'20169,230,635'Memory parametric improvements'20169,170,878'Memory buffer with data scrambling and error correction'20159,171,585'Configurable memory circuit system and method'20159,142,279'DRAM refresh method and system'20159,123,441'Backward compatible dynamic random access memory device and method of testing therefor'20159,069,717'Memory parametric improvements'20159,047,976'Combined signal delay and power saving for use with a plurality of memory circuits'20159,015,558'Systems and methods for error detection and correction in a memory module which includes a memory buffer'20159,001,567'Replacement of a faulty memory cell with a spare cell for a memory circuit'20158,996,960'Vertical error correction code for DRAM memory'20158,972,673'Power management of memory circuits by virtual memory simulation'20158,971,094'Replacement of a faulty memory cell with a spare cell for a memory circuit'20158,966,327'Protocol checking logic circuit for memory system reliability'20158,949,519'Simulating a memory circuit'20158,902,638'Replacement of a faulty memory cell with a spare cell for a memory circuit'20148,879,348'Power management in semiconductor memory system'20148,868,829'Memory circuit system and method'20148,861,277'Method of using non-volatile memories for on-DIMM memory address list storage'20148,854,908'System and method for memory access in server communications'20148,819,356'Configurable multirank memory system with interface circuit'20148,811,065'Performing error detection on DRAMs'20148,797,779'Memory module with memory stack and interface with enhanced capabilites'20148,773,937'Memory refresh apparatus and method'20148,762,675'Memory system for synchronous data transmission'20148,745,321'Simulating a memory standard'20148,711,647'DRAM refresh method and system'20148,710,862'Programming of DIMM termination resistance values'20148,694,857'Systems and methods for error detection and correction in a memory module which includes a memory buffer'20148,687,451'Power management in semiconductor memory system'20148,671,244'Simulating a memory standard'20148,667,312'Performing power management operations'20148,631,193'Emulation of abstracted DIMMS using abstracted DRAMS'20148,631,220'Adjusting the timing of signals associated with a memory system'20148,619,452'Methods and apparatus of stacking DRAMs'20138,601,204'Simulating a refresh operation latency'20138,595,419'Memory apparatus operable to perform a power-saving operation'20138,566,516'Refresh management of memory modules'20138,566,556'Memory module with memory stack and interface with enhanced capabilities'20138,438,328'Emulation of abstracted DIMMs using abstracted DRAMs'20138,407,412'Power management of memory circuits by virtual memory simulation'20138,386,722'Stacked DIMM memory interface'20138,359,187'Simulating a different number of memory circuit devices'20138,340,953'Memory circuit simulation with power saving capabilities'20128,335,894'Configurable memory system with interface circuit'20128,327,104'Adjusting the timing of signals associated with a memory system'20128,280,714'Memory circuit simulation system and method with refresh capabilities'20128,244,971'Memory circuit system and method'20128,209,479'Memory circuit system and method'20128,181,048'Performing power management operations'20128,169,233'Programming of DIMM termination resistance values'20128,154,935'Delaying a signal communicated from a system to at least one of a plurality of memory circuits'20128,122,207'Apparatus and method for power management of memory circuits by a system or component thereof'20128,112,266'Apparatus for simulating an aspect of a memory circuit'20128,089,795'Memory module with memory stack and interface with enhanced capabilities'20128,090,897'System and method for simulating an aspect of a memory circuit'20128,080,874'Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween'20118,077,535'Memory refresh apparatus and method'20118,041,881'Memory device with emulated characteristics'20118,019,589'Memory apparatus operable to perform a power-saving operation'20117,761,724'Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit'20107,730,338'Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits'20107,724,589'System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits'20107,609,567'System and method for simulating an aspect of a memory circuit'20097,590,796'System and method for power management in memory systems'20097,580,312'Power saving system and method for use with a plurality of memory circuits'20097,581,127'Interface circuit system and method for performing power saving operations during a command-related latency'20097,543,102'System and method for performing multi-rank command scheduling in DDR SDRAM memory systems'20097,472,220'Interface circuit system and method for performing power management operations utilizing power management signals'20087,392,338'Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits'20087,386,656'Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit'20085,490,257'RAM based FIFO memory half-full detection apparatus and method'19964,805,149'Digital memory with reset/preset capabilities'19894,740,971'Tag buffer with testing capability'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008–2017Based in San Jose, CA, US· patent location history
2009Based in Gaithersburg, MD, US· patent location history
2010–2017Patents assigned to GOOGLE INC (50)· patent assignee history
2011–2017Patents assigned to WANG DAVID T (44)· patent assignee history
2011–2017Patents assigned to RAJAN SURESH NATARAJAN (39)· patent assignee history
2011–2017Patents assigned to SMITH MICHAEL JOHN SEBASTIAN (30)· patent assignee history
2011–2017Patents assigned to SCHAKEL KEITH R (27)· patent assignee history
2012–2018Based in Thousand Oaks, CA, US· patent location history
2014–2019Based in Santa Clara, CA, US· patent location history
2015–2020Based in Westlake Village, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
GOOGLE INC502010–2017
WANG DAVID Tself442011–2017
RAJAN SURESH NATARAJAN392011–2017
SMITH MICHAEL JOHN SEBASTIAN302011–2017
SCHAKEL KEITH R272011–2017
Locations
LocationPatentsSpan
San Jose, California, US402008–2017
Thousand Oaks, California, US242012–2018
Santa Clara, California, US152014–2019
Westlake Village, California, US72015–2020
Gaithersburg, Maryland, US12009