Inventor
HUAI-TEI YANG
Inventor
TW
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices27%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10DInorganic electric semiconductor devices23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
C23CCoating metallic material4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
B01DSeparation2%
H01JElectric discharge tubes or discharge lamps2%
B24BMachines, devices, or processes for grinding or polishing1%
H05GX-ray technique1%
PatentTitleYear
12,527,041Method of forming source/drain epitaxial stacks202612,490,508Semiconductor device and method202512,446,255Semiconductor structure with source/drain multi-layer structure and method for forming the same202512,394,624Silicon intermixing layer for blocking diffusion202512,371,780Vacuum systems in semiconductor fabrication facilities202512,170,202Formation and in-situ etching processes for metal layers202412,080,761Fully strained channel202412,080,582Etching apparatus and methods of cleaning thereof202412,021,143P-type strained channel in a fin field effect transistor (FinFET) device202412,021,142Method of forming source/drain epitaxial stacks202412,015,055Doping for semiconductor device with conductive feature202411,990,550Semiconductor structure with source/drain multi-layer structure and method for forming the same202411,973,127Semiconductor structure with source/drain structure having modified shape202411,854,811FinFET device and method of forming202311,817,499P-type strained channel in a fin field effect transistor (FinFET) device202311,742,386Doping for semiconductor device with conductive feature202311,685,015Method and system for performing chemical mechanical polishing202311,587,791Silicon intermixing layer for blocking diffusion202311,569,383Method of forming source/drain epitaxial stacks202311,545,363Formation and in-situ etching processes for metal layers202311,526,073Pellicle and method of manufacturing same202211,525,185Vacuum systems in semiconductor fabrication facilities202211,527,655Semiconductor structure with source/drain multi-layer structure and method for forming the same202211,450,741Doping for semiconductor device with conductive feature202211,404,574P-type strained channel in a fin field effect transistor (FinFET) device202211,398,482Semiconductor device and method202211,340,525Pellicle and method of manufacturing same202211,233,123Fully strained channel202211,227,951Method of forming semiconductor device202211,222,805Etching apparatus and methods of cleaning thereof202211,219,115EUV collector contamination prevention202211,195,931Gate structure, semiconductor device and the method of forming semiconductor device2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (31)· patent assignee history
2021–2026Based in TW· patent location history
2025Patents assigned to PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC (1)· patent assignee history
2025Patents assigned to Parabellum Strategic Oppurtunities Fund LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 31 | 2021–2026 |
| PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC | 1 | 2025 |
| Parabellum Strategic Oppurtunities Fund LLC | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 32 | 2021–2026 |