Inventor
Lung T. Tran
Inventor
Saratoga, CA, US
Overview
Patents· 94 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores48%
H10BElectronic memory devices13%
B82YSpecific uses or applications of nanostructures10%
H10NElectric solid-state devices not otherwise provided for7%
H01FMagnets5%
G11BInformation storage based on relative movement between record carrier and transducer3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
G03GElectrography1%
H03FAmplifiers1%
H04LTransmission of digital information, e.g. telegraphic communication1%
PatentTitleYear
11,071,710Licorice extract synergy with menthol for breath freshening in a confectionary product202110,956,380System and method for parallel support of multidimensional slices with a multidimensional database20217,668,487'Printed circuit board printing system'20107,560,215'Printed circuit board printing system and method using liquid electrophotographic printing'20097,557,782'Display device including variable optical element and programmable resistance element'20097,457,153'Integrated circuit memory devices having magnetic memory cells therein that utilize dual-ferromagnetic data layers'20087,391,641'Multi-layered magnetic memory structures'20087,376,004'Increased magnetic memory array sizes and operating margins'20087,339,817'Thermally-assisted switching of magnetic memory elements'20087,267,997'Process for forming magnetic memory structures'20077,196,957'Magnetic memory structure using heater lines to assist in writing operations'20077,180,770'Series diode thermally assisted MRAM'20077,136,300'Magnetic memory device including groups of series-connected memory elements'20067,057,258'Resistive memory device and method for making the same'20067,057,920'Two conductor thermally assisted magnetic memory'20067,038,878'Micromover configured to move a magnetic storage medium in perpendicular directions in a plane'20067,027,319'Retrieving data stored in a magnetic integrated memory'20067,002,820'Semiconductor storage device'20066,967,350'Memory structures'20056,961,263'Memory device with a thermally assisted write'20056,925,003'Magnetic memory cell structure'20056,924,539'Magnetic memory cell having an annular data layer and a soft reference layer'20056,906,941'Magnetic memory structure'20056,903,403'Magnetic memory cell having an annular data layer and a soft reference layer'20056,891,212'Magnetic memory device having soft reference layer'20056,891,746'Magneto-resistive device having soft reference layer'20056,885,573'Diode for use in MRAM devices and method of manufacture'20056,879,508'Memory device array having a pair of magnetic bits sharing a common conductor line'20056,873,544'Triple sample sensing for magnetic random access memory (MRAM) with series diodes'20056,865,105'Thermal-assisted switching array configuration for MRAM'20056,850,433'Magnetic memory device and method'20056,842,389'System for and method of four-conductor magnetic random access memory cell and decoding scheme'20056,839,270'System for and method of accessing a four-conductor magnetic random access memory'20056,828,610'Method for modifying switching field characteristics of magnetic tunnel junctions'20046,826,079'Method and system for performing equipotential sensing across a memory array to eliminate leakage currents'20046,803,274'Magnetic memory cell having an annular data layer and a soft reference layer'20046,801,451'Magnetic memory devices having multiple bits per memory cell'20046,795,281'Magneto-resistive device including soft synthetic ferrimagnet reference layer'20046,791,874'Memory device capable of calibration and calibration methods therefor'20046,791,867'Selection of memory cells in data storage devices'20046,791,865'Memory device capable of calibration and calibration methods therefor'20046,781,906'Memory cell sensing integrator'20046,778,421'Memory device array having a pair of magnetic bits sharing a common conductor line'20046,757,188'Triple sample sensing for magnetic random access memory (MRAM) with series diodes'20046,754,097'Read operations on multi-bit memory cells in resistive cross point arrays'20046,750,491'Magnetic memory device having soft reference layer'20046,727,105'Method of fabricating an MRAM device including spin dependent tunneling junction memory cells'20046,693,825'Magneto-resistive device including clad conductor'20046,678,189'Method and system for performing equipotential sensing across a memory array to eliminate leakage currents'20046,673,714'Method of fabricating a sub-lithographic sized via'20046,649,423'Method for modifying switching field characteristics of magnetic tunnel junctions'20036,639,859'Test array and method for testing memory arrays'20036,625,059'Synthetic ferrimagnet reference layer for a magnetic storage device'20036,607,924'Solid-state memory with magnetic storage cells'20036,608,790'Write current compensation for temperature variations in memory arrays'20036,603,678'Thermally-assisted switching of magnetic memory elements'20036,597,598'Resistive cross point memory arrays having a charge injection differential sense amplifier'20036,593,608'Magneto resistive storage device having double tunnel junction'20036,584,589'Self-testing of magneto-resistive memory arrays'20036,584,029'One-time programmable memory using fuse/anti-fuse and vertically oriented fuse unit memory cells'20036,576,969'Magneto-resistive device having soft reference layer'20036,577,529'Multi-bit magnetic memory device'20036,577,549'Write current compensation for temperature variations in memory arrays'20036,574,129'Resistive cross point memory cell arrays having a cross-couple latch sense amplifier'20036,567,301'One-time programmable unit memory cell based on vertically oriented fuse and diode and one-time programmable memory using the same'20036,541,792'Memory device having dual tunnel junction memory cells'20036,538,920'Cladded read conductor for a pinned-on-the-fly soft reference layer'20036,538,917'Read methods for magneto-resistive device having soft reference layer'20036,515,896'Memory device with short read time'20036,507,513'Using delayed electrical pulses with magneto-resistive devices'20036,504,221'Magneto-resistive device including soft reference layer having embedded conductors'20036,504,742'3-D memory device for large storage capacity'20036,483,734'Memory device having memory cells capable of four states'20026,473,337'Memory device having memory cells with magnetic tunnel junction and tunnel junction in series'20026,456,524'Hybrid resistive cross point memory cell arrays and methods of making the same'20026,434,048'Pulse train writing of worm storage device'20026,434,060'Write pulse limiting for worm storage device'20026,424,565'Solid-state memory with magnetic storage cells'20026,385,111'Reference signal generation for magnetic random access memory devices'20026,385,079'Methods and structure for maximizing signal to noise ratio in resistive array'20026,363,000'Write circuit for large MRAM arrays'20026,356,477'Cross point memory array including shared devices for blocking sneak path currents'20026,317,376'Reference signal generation for magnetic random access memory devices'20016,262,625'Operational amplifier with digital offset calibration'20016,259,644'Equipotential sense methods for resistive cross point memory cell arrays'20016,256,224'Write circuit for large MRAM arrays'20016,188,615'MRAM device including digital sense amplifiers'20016,185,143'Magnetic random access memory (MRAM) device including differential sense amplifiers'20016,169,686'Solid-state memory with magnetic storage cells'20016,163,477'MRAM device using magnetic field bias to improve reproducibility of memory cell switching'20006,111,783'MRAM device including write circuit for supplying word and bit line current having unequal magnitudes'20005,930,087'Robust recording head for near-contact operation'19995,309,304'Magnetoresistive transducer conductor configuration'19944,878,140'Magneto-resistive sensor with opposing currents for reading perpendicularly recorded media'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–2003Patents assigned to HEWLETT PACKARD CO (27)· patent assignee history
1989–2021Based in San Jose, CA, US· patent location history
1994–2010Based in Saratoga, CA, US· patent location history
2003–2010Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (56)· patent assignee history
2003–2005Patents assigned to HEWLETT PACKARD COMPANY L P (2)· patent assignee history
2003Patents assigned to HEWLETT PACKARD DEV COMPANY LL (1)· patent assignee history
2006Based in Sarratoga, CA, US· patent location history
2007–2008Patents assigned to SAMSUNG ELECTRONICS CO LTD (5)· patent assignee history
2021Based in Chicago, IL, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HEWLETT PACKARD DEVELOPMENT CO | 56 | 2003–2010 |
| HEWLETT PACKARD CO | 27 | 1989–2003 |
| SAMSUNG ELECTRONICS CO LTD | 5 | 2007–2008 |
| HEWLETT PACKARD COMPANY L P | 2 | 2003–2005 |
| HEWLETT PACKARD DEV COMPANY LL | 1 | 2003 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga, California, US | 90 | 1994–2010 |
| San Jose, California, US | 2 | 1989–2021 |
| Chicago, Illinois, US | 1 | 2021 |
| Sarratoga, California, US | 1 | 2006 |