Inventor

Charles P. Roth

Inventor

Austin, TX, US

Overview

1997–2020

Patent span

Physics

Primary field (CPC G)

Patents· 63 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing95%

G01RMeasuring electric variables2%

H04LTransmission of digital information, e.g. telegraphic communication2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

10,877,755Processor load using a bit vector to calculate effective address2020 10,216,515Processor load using a bit vector to calculate effective address2019 7,472,259'Multi-cycle instructions'2008 7,366,876'Efficient emulation instruction dispatch based on instruction width'2008 7,360,059'Variable width alignment engine for aligning instructions based on transition between buffers'2008 7,272,705'Early exception detection'2007 7,168,032'Data synchronization for a test access port'2007 7,155,570'FIFO write/LIFO read trace buffer with software and hardware loop compression'2006 7,100,033'Controlling the timing of test modes in a multiple processor system'2006 7,082,516'Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanism'2006 7,069,420'Decode and dispatch of multi-issue and multiple width instructions'2006 7,065,636'Hardware loops and pipeline system using advanced generation of loop parameters'2006 7,043,582'Self-nesting interrupts'2006 7,036,000'Valid bit generation and tracking in a pipelined processor'2006 7,028,165'Processor stalling'2006 6,986,026'Single-step processing and selecting debugging modes'2006 6,976,151'Decoding an instruction portion and forwarding part of the portion to a first destination, re-encoding a different part of the portion and forwarding to a second destination'2005 6,948,056'Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages'2005 6,920,547'Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processor'2005 6,920,515'Early exception detection'2005 6,898,693'Hardware loops'2005 6,842,812'Event handling'2005 6,829,701'Watchpoint engine for a pipelined processor'2004 6,823,448'Exception handling using an exception pipeline in a pipelined processor'2004 6,789,187'Processor reset and instruction fetches'2004 6,789,184'Instruction address generation and tracking in a pipelined processor'2004 6,766,444'Hardware loops'2004 6,763,453'Security on hardware loops'2004 6,760,800'Event vector table override'2004 6,754,808'Valid bit generation and tracking in a pipelined processor'2004 6,748,523'Hardware loops'2004 6,728,870'Register move operations'2004 6,708,296'Method and system for selecting and distinguishing an event sequence using an effective address in a processing system'2004 6,665,795'Resetting a programmable processor'2003 6,519,620'Saturation select apparatus and method therefor'2003 6,499,116'Performance of data stream touch events'2002 6,499,046'Saturation detection apparatus and method therefor'2002 6,470,440'Vector compare and maximum/minimum generation apparatus and method therefor'2002 6,343,337'Wide shifting in the vector permute unit'2002 6,327,651'Wide shifting in the vector permute unit'2001 6,249,906'Adaptive method and system to minimize the effect of long table walks'2001 6,189,072'Performance monitoring of cache misses and instructions completed for instruction parallelism analysis'2001 6,178,500'Vector packing and saturation detection in the vector permute unit'2001 6,134,710'Adaptive method and system to minimize the effect of long cache misses'2000 6,119,224'Fast shift amount decode for VMX shift and vperm instructions'2000 6,085,338'CPI infinite and finite analysis'2000 6,067,644'System and method monitoring instruction progress within a processor'2000 5,991,708'Performance monitor and method for performance monitoring within a data processing system'1999 5,987,598'Method and system for tracking instruction progress within a data processing system'1999 5,970,439'Performance monitoring in a data processing system'1999 5,961,654'Operand fetch bandwidth analysis'1999 5,949,971'Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system'1999 5,938,760'System and method for performance monitoring of instructions in a re-order buffer'1999 5,937,437'Method and apparatus for monitoring address translation performance'1999 5,881,306'Instruction fetch bandwidth analysis'1999 5,875,294'Method and system for halting processor execution in response to an enumerated occurrence of a selected combination of internal states'1999 5,835,702'Performance monitor'1998 5,802,273'Trailing edge analysis'1998 5,797,019'Method and system for performance monitoring time lengths of disabled interrupts in a processing system'1998 5,751,945'Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system'1998 5,748,855'Method and system for performance monitoring of misaligned memory accesses in a processing system'1998 5,729,726'Method and system for performance monitoring efficiency of branch unit operation in a processing system'1998 5,691,920'Method and system for performance monitoring of dispatch unit efficiency in a processing system'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2004Patents assigned to IBM (29)· patent assignee history

1997–2020Based in Austin, TX, US· patent location history

2001–2002Patents assigned to MOTOROLA INC (2)· patent assignee history

2003–2008Patents assigned to ANALOG DEVICES INC (30)· patent assignee history

2003–2006Patents assigned to INTEL CORP (13)· patent assignee history

2019–2020Patents assigned to ORACLE INT CORP (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ANALOG DEVICES INC	30	2003–2008
IBM	29	1997–2004
INTEL CORP	13	2003–2006
MOTOROLA INC	2	2001–2002
ORACLE INT CORP	2	2019–2020

Locations

Location	Patents	Span
Austin, Texas, US	63	1997–2020