Inventor
Serge Lasserre
Inventor
Frejus, FR
Overview
Patents· 51 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing58%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use29%
G09GArrangements or circuits for control of indicating devices using static means to present variable information5%
H04NPictorial communication, e.g. television4%
H04LTransmission of digital information, e.g. telegraphic communication2%
G11CStatic stores1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
9,141,561'Master circuits having dynamic priority leads coupled with memory controller'20158,539,159'Dirty cache line write back policy based on stack size trend information'20138,429,383'Multi-processor computing system having a JAVA stack machine and a RISC-based processor'20138,190,861'Micro-sequence based security model'20128,156,283'Processing function connected to processor memory hierarchy'20128,032,891'Energy-aware scheduling of application execution'20117,941,790'Data processing apparatus, system and method'20117,840,782'Mixed stack-based RISC processor'20107,840,784'Test and skip processor instruction having at least one register operand'20107,757,067'Pre-decoding bytecode prefixes selectively incrementing stack machine program counter'20107,712,098'Data transfer controlled by task attributes'20107,634,643'Stack register reference control bit in source operand of instruction'20097,565,385'Embedded garbage collection'20097,555,611'Memory management of local variables upon a change of context'20097,509,391'Unified memory management system for multi processor heterogeneous architecture'20097,496,930'Accessing device driver memory in programming language representation'20097,434,021'Memory allocation in a multi-processor system'20087,434,029'Inter-processor control'20087,386,671'Smart cache'20087,360,060'Using IMPDEP2 for system commands related to Java accelerator hardware'20087,330,937'Management of stack-based memory usage in a processor'20087,162,586'Synchronizing stack storage'20077,058,765'Processor with a split stack'20066,996,683'Cache coherency in a multi-processor system'20066,968,400'Local memory with indicator bits to support concurrent DMA and CPU access'20056,934,820'Traffic controller using priority and burst control for reducing access latency'20056,851,072'Fault management and recovery based on task-ID'20056,826,652'Smart cache'20046,792,508'Cache with multiple fill modes'20046,789,172'Cache and DMA with a global valid bit'20046,772,326'Interruptible an re-entrant cache clean range instruction'20046,766,421'Fast hardware looping mechanism for cache cleaning and flushing of cache entries corresponding to a qualifier field'20046,760,829'MMU descriptor having big/little endian bit to control the transfer data between devices'20046,754,781'Cache with DMA and dirty bits'20046,751,706'Multiple microprocessors with a shared cache'20046,745,293'Level 2 smartcache architecture supporting simultaneous multiprocessor accesses'20046,742,103'Processing system with shared translation lookaside buffer'20046,742,104'Master/slave processing system with shared translation lookaside buffer'20046,728,838'Cache operation based on range of addresses'20046,697,916'Cache with block prefetch and DMA'20046,684,280'Task based priority arbitration'20046,681,297'Software controlled cache configuration based on average miss rate'20046,678,797'Cache/smartcache with interruptible block prefetch'20046,606,687'Optimized hardware cleaning function for VIVT data cache'20036,430,664'Digital signal processor with direct and virtual addressing'20026,412,048'Traffic controller using priority and burst control for reducing access latency'20026,369,855'Audio and video decoder circuit and system'20026,321,299'Computer circuits, systems, and methods using partial cache cleaning'20016,310,657'Real time window address calculation for on-screen display'20016,253,297'Memory control using memory state information for reducing access latency'20016,226,291'Transport stream packet parser system'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2015Patents assigned to TEXAS INSTRUMENTS INC (51)· patent assignee history
2001–2013Based in Frejus, FR· patent location history
2005–2015Based in Plascassier, FR· patent location history
2005Based in Cannes, FR· patent location history
2012–2013Patents assigned to CHAUVEL GERARD (3)· patent assignee history
2012–2013Patents assigned to D INVERNO DOMINIQUE (3)· patent assignee history
2012–2013Patents assigned to LASSERRE SERGE (3)· patent assignee history
2012Patents assigned to BADI ERIC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 51 | 2001–2015 |
| CHAUVEL GERARD | 3 | 2012–2013 |
| D INVERNO DOMINIQUE | 3 | 2012–2013 |
| LASSERRE SERGEself | 3 | 2012–2013 |
| BADI ERIC | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Frejus, FR | 43 | 2001–2013 |
| Plascassier, FR | 7 | 2005–2015 |
| Cannes, FR | 1 | 2005 |