Inventor
Christopher M. Abernathy
Inventor
Austin, TX, US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing85%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
G01RMeasuring electric variables2%
H03MCoding2%
PatentTitleYear
10,296,339Thread transition management201910,275,251Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file201910,055,226Thread transition management20189,959,121Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers20189,703,561'Thread transition management'20179,495,490'Active power dissipation detection based on erroneus clock gating equations'20169,286,068'Efficient usage of a multi-level register file utilizing a register file bypass'20168,874,880'Instruction tracking system for processors'20148,725,993'Thread transition management'20148,661,227'Multi-level register file supporting multiple threads'20148,661,228'Multi-level register file supporting multiple threads'20148,631,223'Register file supporting transactional processing'20148,521,998'Instruction tracking system for processors'20138,239,661'System and method for double-issue instructions using a dependency matrix'20128,200,946'Issue unit for placing a processor into a gradual slow mode of operation'20128,135,942'System and method for double-issue instructions using a dependency matrix and a side issue queue'20128,108,655'Selecting fixed-point instructions to issue on load-store unit'20128,099,582'Tracking deallocated load instructions using a dependence matrix'20128,082,423'Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates'20118,046,566'Method to reduce power consumption of a register file with multi SMT support'20118,037,366'Issuing instructions in-order in an out-of-order processor using false dependencies'20118,028,151'Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines'20118,020,072'Method and apparatus for correcting data errors'20117,991,979'Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system'20117,913,070'Time-of-life counter for handling instruction flushes from a queue'20117,900,024'Handling data cache misses out-of-order for asynchronous pipelines'20117,890,782'Dynamic power management in an execution unit using pipeline wave flow control'20117,831,808'Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor'20107,818,544'Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition'20107,769,986'Method and apparatus for register renaming'20107,689,812'Method and system for restoring register mapper states for an out-of-order microprocessor'20107,681,056'Dynamic power management in a processor design'20107,653,848'Selectively engaging optional data reduction mechanisms for capturing trace data'20107,490,224'Time-of-life counter design for handling instruction flushes from a queue'20097,475,232'Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines'20097,469,357'Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control'20087,461,239'Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines'20087,437,539'Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline'20087,434,033'Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline'20087,401,242'Dynamic power management in a processor design'20087,363,469'Method and system for on-demand scratch register renaming'20087,350,056'Method and apparatus for issuing instructions from an issue queue in an information handling system'20087,328,330'Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor'20087,313,673'Fine grained multi-thread dispatch block mechanism'20077,137,013'Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control'20066,934,729'Method and system for performing shift operations'20056,820,227'Method and apparatus for performing error checking'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2019Patents assigned to IBM (47)· patent assignee history
2004–2019Based in Austin, TX, US· patent location history
2012–2016Patents assigned to ABERNATHY CHRISTOPHER M (9)· patent assignee history
2012–2014Patents assigned to BROWN MARY D (7)· patent assignee history
2014Patents assigned to LE HUNG Q (4)· patent assignee history
2014Patents assigned to NGUYEN DUNG Q (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 47 | 2004–2019 |
| ABERNATHY CHRISTOPHER Mself | 9 | 2012–2016 |
| BROWN MARY D | 7 | 2012–2014 |
| LE HUNG Q | 4 | 2014 |
| NGUYEN DUNG Q | 4 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 47 | 2004–2019 |