Inventor
Tae-Joong Song
Inventor
Seongnam-si, KR
Overview
Patents· 56 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores19%
H10DInorganic electric semiconductor devices18%
G06FElectric digital data processing17%
H01LSemiconductor devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
H03KPulse technique4%
H10BElectronic memory devices4%
G16ZInformation and communication technology [ict] specially adapted for specific application fields, not otherwise provided for1%
PatentTitleYear
11,101,803Semiconductor device202111,042,686Integrated circuit including standard cells overlapping each other and method of generating layout of the integrated circuit202111,031,385Standard cell for removing routing interference between adjacent pins and device including the same202110,832,988Integrated circuit having contact jumper202010,811,357Standard cell and an integrated circuit including the same202010,803,971Device for supporting error correction code and test method thereof202010,803,226Integrated circuit for multiple patterning lithography, a computing system and a computer-implemented method for designing an integrated circuit202010,762,958Resistive memory device including a reference cell and method of controlling a reference cell to identify values stored in memory cells202010,726,186Integrated circuit including a modified cell and a method of designing the same202010,672,702Integrated circuit including standard cell202010,651,201Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration202010,600,466Resistive memory device having reduced chip size and operation method thereof202010,579,771Integrated circuit including standard cells overlapping each other and method of generating layout of the integrated circuit202010,573,643Integrated circuit having vertical transistor and semiconductor device including the integrated circuit202010,553,574Standard cell for removing routing interference between adjacent pins and device including the same202010,445,455Integrated circuit for multiple patterning lithography, a computing system and a computer-implemented method for designing an integrated circuit201910,373,664Resistive memory device having reduced chip size and operation method thereof201910,354,947Integrated circuit including standard cell201910,319,668Integrated circuit having contact jumper201910,311,946Semiconductor memory device with assymetric precharge201910,216,883Integrated circuit and method of designing integrated circuit201910,083,966Semiconductor integrated circuits having contacts spaced apart from active regions201810,020,048Integrated circuit including embedded memory device for performing dual-transient word line assist using triple power source and device having the same20189,905,561'Integrated circuit and semiconductor device'20189,852,252Standard cell library and methods of using the same20179,842,182'Method and system for designing semiconductor device'20179,830,415Standard cell library, method of using the same, and method of designing semiconductor integrated circuit20179,748,246'Semiconductor integrated circuits having contacts spaced apart from active regions'20179,633,161'Layout design system, method, and semiconductor device employing termination-free unit designs'20179,627,376'Semiconductor device with active fins separated by shallow and deep trench isolations and method for fabricating the same'20179,583,493'Integrated circuit and semiconductor device'20179,576,953'Layout design system, semiconductor device fabricated by using the system and method for fabricating the semiconductor device'20179,436,792'Method of designing layout of integrated circuit and method of manufacturing integrated circuit'20169,324,384'Sense amplifiers and memory devices having the same'20169,306,070'Semiconductor device and method of fabricating the same'20169,299,711'Field effect transistors including asymmetrical silicide structures and related devices'20169,240,223'Semiconductor memory devices with a power supply'20169,098,670'Double patterning layout design method'20159,087,566'Semiconductor memory devices including a discharge circuit'20159,026,975'Semiconductor integrated circuit, method of designing the same, and method of fabricating the same'20158,934,313'Negative voltage generator and semiconductor memory device'20158,743,646'Semiconductor memory devices with a power supply'20147,359,266'Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same'20087,349,274'Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same'20087,203,110'Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same'20077,170,805'Memory devices having bit line precharge circuits with off current precharge control and associated bit line precharge methods'20077,110,317'SRAM employing virtual rail scheme stable against various process-voltage-temperature variations'20067,095,665'Sense amplifier driver and semiconductor device comprising the same'20067,057,420'Semiconductor device having sense amplifier driver with capacitor affected by off current'20067,012,847'Sense amplifier driver and semiconductor device comprising the same'20066,996,019'Semiconductor device having sense amplifier driver that controls enabling timing'20066,952,363'Semiconductor memory device with selectively connectable segmented bit line member and method of driving the same'20056,862,245'Dual port static memory cell and semiconductor memory device having the same'20056,741,508'Sense amplifier driver circuits configured to track changes in memory cell pass transistor characteristics'20046,614,710'Semiconductor memory device and data read method thereof'20036,480,037'Sense amplifier circuit of semiconductor memory device'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2021Patents assigned to SAMSUNG ELECTRONICS CO LTD (56)· patent assignee history
2002–2003Based in Suwon-si, KR· patent location history
2004–2007Based in Kyungki-do, KR· patent location history
2005–2006Based in Gyeonggi-do, KR· patent location history
2007–2008Based in Hwaseong-si, KR· patent location history
2014–2017Patents assigned to SONG TAE-JOONG (6)· patent assignee history
2014–2021Based in Seongnam-si, KR· patent location history
2015Patents assigned to JUNG JONG-HOON (2)· patent assignee history
2015Patents assigned to KIM GYU-HONG (2)· patent assignee history
2017Patents assigned to BAEK KANG-HYUN (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 56 | 2002–2021 |
| SONG TAE-JOONGself | 6 | 2014–2017 |
| JUNG JONG-HOON | 2 | 2015 |
| KIM GYU-HONG | 2 | 2015 |
| BAEK KANG-HYUN | 1 | 2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Seongnam-si, KR | 42 | 2014–2021 |
| Gyeonggi-do, KR | 6 | 2005–2006 |
| Hwaseong-si, KR | 3 | 2007–2008 |
| Kyungki-do, KR | 2 | 2004–2007 |
| Suwon-si, KR | 2 | 2002–2003 |