Inventor

Brandon P. Wirz

Inventor

Boise, ID, US

Overview

16→

Patents

2015–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 16 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices38%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%

B29CShaping or joining of plastics2%

B29KIndexing scheme associated with subclasses b29b, b29c or b29d, relating to moulding materials or to materials for moulds, reinforcements, fillers or preformed parts, e.g. inserts2%

B29LIndexing scheme associated with subclass b29c, relating to particular articles2%

B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

Y10TTechnical subjects covered by former us classification2%

PatentTitleYear

11,024,595Thermocompression bond tips and related apparatus and methods2021 11,004,828Methods and apparatus for integrated gang bonding and encapsulation of stacked microelectronic devices2021 10,950,568Semiconductor device assembly with surface-mount die support structures2021 10,923,447Semiconductor device assembly with die support structures2021 10,879,195Method for substrate moisture NCF voiding elimination2020 10,825,761Electronic devices having tapered edge walls2020 10,825,762Methods of processing semiconductor devices2020 10,276,539Method for 3D ink jet TCB interconnect control2019 10,276,479Methods of processing semiconductor devices2019 10,043,688Method for mount tape die release system for thin die ejection2018 9,966,347Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods2018 9,741,612'Semiconductor devices and methods for backside photo alignment'2017 9,704,781'Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods'2017 9,362,143'Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages'2016 9,299,663'Semiconductor devices and methods for backside photo alignment'2016 9,123,700'Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias'2015

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2015–2021Patents assigned to MICRON TECHNOLOGY INC (16)· patent assignee history

2015–2016Patents assigned to GANDHI JASPREET S (2)· patent assignee history

2015–2016Patents assigned to SUN YANGYANG (2)· patent assignee history

2015–2016Patents assigned to WIRZ BRANDON P (2)· patent assignee history

2015–2016Patents assigned to WOODLAND JOSH D (2)· patent assignee history

2015–2018Based in Kuna, ID, US· patent location history

2018–2021Based in Boise, ID, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	16	2015–2021
GANDHI JASPREET S	2	2015–2016
SUN YANGYANG	2	2015–2016
WIRZ BRANDON Pself	2	2015–2016
WOODLAND JOSH D	2	2015–2016

Locations

Location	Patents	Span
Boise, ID, US	10	2018–2021
Kuna, ID, US	6	2015–2018