Inventor
Gen Tada
Inventor
Nagano, JP
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices52%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
G09GArrangements or circuits for control of indicating devices using static means to present variable information10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
F16BDevices for fastening or securing constructional elements or machine parts together, e.g. nails, bolts, circlips, clamps, clips or wedges3%
G09FDisplaying3%
H01JElectric discharge tubes or discharge lamps3%
H01LSemiconductor devices3%
PatentTitleYear
9,401,319'Semiconductor device'20167,876,291'Drive device'20117,714,363'Semiconductor integrated circuit for driving the address of a display device'20107,687,385'Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same'20107,606,082'Semiconductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof'20097,195,980'Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same'20077,173,454'Display device driver circuit'20076,853,034'Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same'20056,844,598'Lateral high breakdown voltage MOSFET and device provided therewith'20056,818,954'Lateral high breakdown voltage MOSFET and device provided therewith'20046,740,952'High withstand voltage semiconductor device'20046,558,983'Semiconductor apparatus and method for manufacturing the same'20036,525,390'MIS semiconductor device with low on resistance and high breakdown voltage'20036,316,794'Lateral high voltage semiconductor device with protective silicon nitride film in voltage withstanding region'20015,973,366'High voltage integrated circuit'19995,612,564'Semiconductor device with limiter diode'19975,545,577'Method of producing a semiconductor device having two MIS transistor circuits'19965,497,021'CMOS structure with varying gate oxide thickness and with both different and like conductivity-type gate electrodes'19965,495,122'Insulated-gate semiconductor field effect transistor which operates with a low gate voltage and high drain and source voltages'19965,436,486'High voltage MIS transistor and semiconductor device'19955,432,370'High withstand voltage M I S field effect transistor and semiconductor integrated circuit'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2007Patents assigned to FUJI ELECTRIC CO LTD (15)· patent assignee history
1995–1997Based in Kawasaki, JP· patent location history
1999–2011Based in Nagano, JP· patent location history
2007–2010Patents assigned to FUJI ELEC DEVICE TECH CO LTD (3)· patent assignee history
2007Based in Tokyo, JP· patent location history
2009–2010Based in Matsumoto, JP· patent location history
2010Patents assigned to FUJI ELECTRIC HOLDINGS (1)· patent assignee history
2011Patents assigned to FUJI ELECTRIC SYSTEMS CO LTD (1)· patent assignee history
2016Patents assigned to JIDA TSUYOSHI (1)· patent assignee history
2016Based in Chiyoda-ku, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FUJI ELECTRIC CO LTD | 15 | 1995–2007 |
| FUJI ELEC DEVICE TECH CO LTD | 3 | 2007–2010 |
| FUJI ELECTRIC HOLDINGS | 1 | 2010 |
| FUJI ELECTRIC SYSTEMS CO LTD | 1 | 2011 |
| JIDA TSUYOSHI | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Nagano, JP | 11 | 1999–2011 |
| Kawasaki, JP | 6 | 1995–1997 |
| Matsumoto, JP | 2 | 2009–2010 |
| Chiyoda-ku, JP | 1 | 2016 |
| Tokyo, JP | 1 | 2007 |