Inventor

John Steven Dodson

Inventor

Pflugerville, TX, US

Overview

1996–2021

Patent span

Physics

Primary field (CPC G)

Patents· 243 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing88%

G11CStatic stores8%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

H03KPulse technique0%

H04LTransmission of digital information, e.g. telegraphic communication0%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications0%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests0%

PatentTitleYear

11,017,875Tracking address ranges for computer memory errors2021 10,971,246Performing error correction in computer memory2021 10,949,346Data flush of a persistent memory cache or buffer2021 10,353,669Managing entries in a mark table of computer memory errors2019 10,338,999Confirming memory marks indicating an error in computer memory2019 10,304,560Performing error correction in computer memory2019 10,297,335Tracking address ranges for computer memory errors2019 10,176,125Dynamically adjusting read data return sizes based on interconnect bus utilization2019 10,019,370Probabilistic associative cache2018 9,892,066'Dynamically adjusting read data return sizes based on interconnect bus utilization'2018 9,684,461'Dynamically adjusting read data return sizes based on memory interface bus utilization'2017 9,632,954'Memory queue handling techniques for reducing impact of high-latency memory operations'2017 9,594,647'Synchronization and order detection in a memory system'2017 9,594,646'Reestablishing synchronization in a memory system'2017 9,568,986'System-wide power conservation using memory cache'2017 9,535,778'Reestablishing synchronization in a memory system'2017 9,495,254'Synchronization and order detection in a memory system'2016 9,495,231'Reestablishing synchronization in a memory system'2016 9,471,410'Transient condition management utilizing a posted error detection processing protocol'2016 9,430,418'Synchronization and order detection in a memory system'2016 9,424,194'Probabilistic associative cache'2016 9,384,136'Modification of prefetch depth based on high latency event'2016 9,378,144'Modification of prefetch depth based on high latency event'2016 9,128,834'Implementing memory module communications with a host processor in multiported memory configurations'2015 9,086,997'Memory uncorrectable error handling technique for reducing the impact of noise'2015 9,086,998'Memory uncorrectable error handling technique for reducing the impact of noise'2015 9,058,178'Selective posted data error detection based on request type'2015 9,058,260'Transient condition management utilizing a posted error detection processing protocol'2015 8,996,824'Memory reorder queue biasing preceding high latency operations'2015 8,990,640'Selective posted data error detection based on request type'2015 8,909,874'Memory reorder queue biasing preceding high latency operations'2014 8,867,304'Command throttling for multi-channel duty-cycle based memory power management'2014 8,862,944'Isolation of faulty links in a transmission medium'2014 8,775,906'Efficient storage of meta-bits within a system memory'2014 8,775,904'Efficient storage of meta-bits within a system memory'2014 8,675,444'Synchronized command throttling for multi-channel duty-cycle based memory power management'2014 8,635,401'Method and apparatus for performing refresh operations in high-density memories'2014 8,543,759'Method for scheduling memory refresh operations including power states'2013 8,539,146'Apparatus for scheduling memory refresh operations including power states'2013 8,489,807'Techniques for performing refresh operations in high-density memories'2013 7,302,616'Method and apparatus for performing bus tracing with scalable bandwidth in a data processing system having a distributed memory'2007 7,284,097'Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes'2007 7,213,169'Method and apparatus for performing imprecise bus tracing in a data processing system having a distributed memory'2007 7,058,767'Adaptive memory access speculation'2006 7,017,024'Data processing system having no system memory'2006 6,970,976'Layered local cache with lower level cache optimizing allocation mechanism'2005 6,963,967'System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture'2005 6,920,521'Method and system of managing virtualized physical memory in a data processing system'2005 6,907,494'Method and system of managing virtualized physical memory in a memory controller and processor system'2005 6,904,490'Method and system of managing virtualized physical memory in a multi-processor system'2005 6,901,485'Memory directory management in a multi-node computer system'2005 6,886,079'Dynamic history based mechanism for the granting of exclusive data ownership in a non-uniform memory access (NUMA) computer system'2005 6,880,073'Speculative execution of instructions and processes before completion of preceding barrier operations'2005 6,801,984'Imprecise snooping based invalidation mechanism'2004 6,763,434'Data processing system and method for resolving a conflict between requests to modify a shared cache line'2004 6,763,433'High performance cache intervention mechanism for symmetric multiprocessor systems'2004 6,760,817'Method and system for prefetching utilizing memory initiated prefetch write operations'2004 6,760,809'Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memory'2004 6,754,782'Decentralized global coherency management in a multi-node computer system'2004 6,748,518'Multi-level multiprocessor speculation mechanism'2004 6,728,873'System and method for providing multiprocessor speculation within a speculative branch path'2004 6,725,340'Mechanism for folding storage barrier operations in a multiprocessor system'2004 6,721,853'High performance data processing system via cache victimization protocols'2004 6,721,856'Enhanced cache management mechanism via an intelligent system bus monitor'2004 6,711,652'Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data'2004 6,704,843'Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange'2004 6,701,416'Cache coherency protocol with tagged intervention of modified values'2004 6,691,220'Multiprocessor speculation mechanism via a barrier speculation flag'2004 6,662,275'Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache'2003 6,662,216'Fixed bus tags for SMP buses'2003 6,658,538'Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control'2003 6,658,536'Cache-coherency protocol with recently read state for extending cache horizontally'2003 6,654,857'Non-uniform memory access (NUMA) computer system having distributed global coherency management'2003 6,633,959'Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data'2003 6,631,450'Symmetric multiprocessor address bus protocol with intra-cache line access information'2003 6,629,212'High speed lock acquisition mechanism with time parameterized cache coherency states'2003 6,629,209'Cache coherency protocol permitting sharing of a locked data granule'2003 6,629,210'Intelligent cache management mechanism via processor access sequence analysis'2003 6,629,214'Extended cache coherency protocol with a persistent lock acquired state'2003 6,625,660'Multiprocessor speculation mechanism for efficiently managing multiple barrier operations'2003 6,625,701'Extended cache coherency protocol with a modified store instruction lock release indicator'2003 6,615,321'Mechanism for collapsing store misses in an SMP computer system'2003 6,615,322'Two-stage request protocol for accessing remote memory data in a NUMA data processing system'2003 6,615,320'Store collapsing mechanism for SMP computer system'2003 6,609,192'System and method for asynchronously overlapping storage barrier operations with old and new storage operations'2003 6,606,702'Multiprocessor speculation mechanism with imprecise recycling of storage operations'2003 6,601,144'Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis'2003 6,587,924'Scarfing within a hierarchical memory architecture'2003 6,587,926'Incremental tag build for hierarchical memory architecture'2003 6,587,925'Elimination of vertical bus queueing within a hierarchical memory architecture'2003 6,581,139'Set-associative cache memory having asymmetric latency among sets'2003 6,574,714'Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache'2003 6,571,322'Multiprocessor computer system with sectored cache line mechanism for cache intervention'2003 6,553,442'Bus master for SMP execution of global operations utilizing a single token with implied release'2003 6,553,462'Multiprocessor computer system with sectored cache line mechanism for load and store operations'2003 6,549,989'Extended cache coherency protocol with a lock released state'2003 6,532,521'Mechanism for high performance transfer of speculative request data between levels of cache hierarchy'2003 6,516,368'Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release'2003 6,510,494'Time based mechanism for cached speculative data deallocation'2003 6,507,880'Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens'2003 6,505,277'Method for just-in-time delivery of load data by intervening caches'2003 6,502,168'Cache having virtual cache controller queues'2002 6,502,171'Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data'2002 6,496,921'Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions'2002 6,487,637'Method and system for clearing dependent speculations from a request queue'2002 6,484,241'Multiprocessor computer system with sectored cache line system bus protocol mechanism'2002 6,480,975'ECC mechanism for set associative cache array'2002 6,480,915'Bus protocol and token manager for SMP execution of global operations utilizing a single token with implied release'2002 6,477,613'Cache index based system address bus'2002 6,470,427'Programmable agent and method for managing prefetch queues'2002 6,463,507'Layered local cache with lower level cache updating upper and lower level cache directories'2002 6,460,117'Set-associative cache memory having a mechanism for migrating a most recently used set'2002 6,460,118'Set-associative cache memory having incremental access latencies among sets'2002 6,460,100'Bus snooper for SMP execution of global operations utilizing a single token with implied release'2002 6,460,101'Token manager for execution of global operations utilizing multiple tokens'2002 6,446,166'Method for upper level cache victim selection management by a lower level cache'2002 6,442,629'Bus protocol and token manager for execution of global operations utilizing a single token with multiple operations with explicit release'2002 6,438,656'Method and system for cancelling speculative cache prefetch requests'2002 6,434,667'Layered local cache with imprecise reload mechanism'2002 6,434,670'Method and apparatus for efficiently managing caches with non-power-of-two congruence classes'2002 6,430,683'Processor and method for just-in-time delivery of load data via time dependency field'2002 6,427,204'Method for just in-time delivery of instructions in a data processing system'2002 6,425,090'Method for just-in-time delivery of load data utilizing alternating time intervals'2002 6,421,763'Method for instruction extensions for a tightly coupled speculative request unit'2002 6,421,762'Cache allocation policy based on speculative request history'2002 6,418,514'Removal of posted operations from cache operations queue'2002 6,418,516'Method and system for managing speculative requests in a multi-level memory hierarchy'2002 6,418,513'Queue-less and state-less layered local data cache mechanism'2002 6,415,358'Cache coherency protocol having an imprecise hovering (H) state for instructions and data'2002 6,405,285'Layered local cache mechanism with split register load bus and cache load bus'2002 6,397,320'Method for just-in-time delivery of load data via cycle of dependency'2002 6,397,300'High performance store instruction management via imprecise local cache update mechanism'2002 6,397,298'Cache memory having a programmable cache replacement scheme'2002 6,393,553'Acknowledgement mechanism for just-in-time delivery of load data'2002 6,393,528'Optimized cache allocation algorithm for multiple speculative requests'2002 6,389,529'Method for alternate preferred time delivery of load data'2002 6,385,694'High performance load instruction management via system bus with explicit register load and/or cache reload protocols'2002 6,385,702'High performance multiprocessor system with exclusive-deallocate cache state'2002 6,374,333'Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention'2002 6,374,330'Cache-coherency protocol with upstream undefined state'2002 6,360,299'Extended cache state with prefetched stream ID information'2002 6,353,875'Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions'2002 6,349,367'Method and system for communication in which a castout operation is cancelled in response to snoop responses'2002 6,349,369'Protocol for transferring modified-unsolicited state during data intervention'2002 6,347,361'Cache coherency protocols with posted operations'2002 6,347,363'Merged vertical cache controller mechanism with combined cache controller and snoop queries for in-line caches'2002 6,345,342'Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line'2002 6,345,340'Cache coherency protocol with ambiguous state for posted operations'2002 6,345,343'Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state'2002 6,345,339'Pseudo precise I-cache inclusivity for vertical caches'2002 6,345,344'Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits'2002 6,343,344'System bus directory snooping mechanism for read/castout (RCO) address transaction'2002 6,343,347'Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction'2002 6,341,336'Cache coherency protocol having tagged state used with cross-bars'2002 6,338,124'Multiprocessor system bus with system controller explicitly updating snooper LRU information'2002 6,334,172'Cache coherency protocol with tagged state for modified values'2001 6,330,643'Cache coherency protocols with global and local posted operations'2001 6,324,617'Method and system for communicating tags of data access target and castout victim in a single data transfer'2001 6,321,305'Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data'2001 6,321,306'High performance multiprocessor system with modified-unsolicited cache state'2001 6,314,498'Multiprocessor system bus transaction for transferring exclusive-deallocate cache state to lower lever cache'2001 6,292,872'Cache coherency protocol having hovering (H) and recent (R) states'2001 6,279,086'Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position'2001 6,275,908'Cache coherency protocol including an HR state'2001 6,275,909'Multiprocessor system bus with system controller explicitly updating snooper cache state information'2001 6,272,603'Cache coherency protocol having hovering (H), recent (R), and tagged (T) states'2001 6,263,407'Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode'2001 6,247,098'Cache coherency protocol with selectively implemented tagged state'2001 6,212,605'Eviction override for larx-reserved addresses'2001 6,212,616'Even/odd cache directory mechanism'2001 6,195,729'Deallocation with cache update protocol (L2 evictions)'2001 6,192,458'High performance cache directory addressing scheme for variable cache sizes utilizing associativity'2001 6,192,451'Cache coherency protocol for a data processing system including a multi-level memory hierarchy'2001 6,185,658'Cache with enhanced victim selection using the coherency states of cache lines'2001 6,182,201'Demand-based issuance of cache operations to a system bus'2001 6,178,484'DCBST with ICBI mechanism to maintain coherency of bifurcated data and instruction caches'2001 6,175,930'Demand based sync bus operation'2001 6,173,371'Demand-based issuance of cache operations to a processor bus'2001 6,157,980'Cache directory addressing scheme for variable cache sizes'2000 6,145,038'Method and system for early slave forwarding of strictly ordered bus operations'2000 6,145,057'Precise method and system for selecting an alternative cache entry for replacement in response to a conflict between cache operation requests'2000 6,145,059'Cache coherency protocols with posted operations and tagged coherency states'2000 6,141,733'Cache coherency protocol with independent implementation of optimized cache operations'2000 6,138,218'Forward progress on retried snoop hits by altering the coherency state of a local cache'2000 6,128,707'Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles'2000 6,122,691'Apparatus and method of layering cache and architectural specific functions to permit generic interface definition'2000 6,115,794'Method and system of providing a pseudo-precise inclusivity scheme in a sectored cache memory for maintaining cache coherency within a data-processing system'2000 6,112,270'Method and system for high speed transferring of strictly ordered bus operations by reissuing bus operations in a multiprocessor system'2000 6,105,112'Dynamic folding of cache operations for multiple coherency-size systems'2000 6,101,582'Dcbst with icbi mechanism'2000 6,094,710'Method and system for increasing system memory bandwidth within a symmetric multiprocessor data-processing system'2000 6,085,288'Dual cache directories with respective queue independently executing its content and allowing staggered write operations'2000 6,078,991'Method and system for speculatively requesting system data bus for sourcing cache memory data within a multiprocessor data-processing system'2000 6,065,086'Demand based sync bus operation'2000 6,061,755'Method of layering cache and architectural specific functions to promote operation symmetry'2000 6,061,762'Apparatus and method for separately layering cache and architectural specific functions in different operational controllers'2000 6,058,456'Software-managed programmable unified/split caching mechanism for instructions and data'2000 6,055,608'Method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system'2000 6,049,849'Imprecise method and system for selecting an alternative cache entry for replacement in response to a conflict between cache operation requests'2000 6,038,642'Method and system for assigning cache memory utilization within a symmetric multiprocessor data-processing system'2000 6,032,226'Method and apparatus for layering cache and architectural specific functions to expedite multiple design'2000 6,029,204'Precise synchronization mechanism for SMP system buses using tagged snoop operations to avoid retries'2000 6,026,470'Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels'2000 6,023,746'Dual associative-cache directories allowing simultaneous read operation using two buses with multiplexors, address tags, memory block control signals, single clock cycle operation and error correction'2000 6,023,747'Method and system for handling conflicts between cache operation requests in a data processing system'2000 6,021,468'Cache coherency protocol with efficient write-through aliasing'2000 6,018,791'Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states'2000 6,006,311'Dynamic updating of repair mask used for cache defect avoidance'1999 6,000,014'Software-managed programmable congruence class caching mechanism'1999 5,996,049'Cache-coherency protocol with recently read state for data and instructions'1999 5,983,322'Hardware-managed programmable congruence class caching mechanism'1999 5,978,888'Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels'1999 5,978,871'Method of layering cache and architectural specific functions for operation splitting'1999 5,974,507'Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm'1999 5,963,974'Cache intervention from a cache line exclusively holding an unmodified value'1999 5,958,068'Cache array defect functional bypassing using repair mask'1999 5,956,503'Method and system for front-end and back-end gathering of store instructions within a data-processing system'1999 5,946,709'Shared intervention protocol for SMP bus using caches, snooping, tags and prioritizing'1999 5,943,684'Method and system of providing a cache-coherency protocol for maintaining cache coherency within a multiprocessor data-processing system'1999 5,943,685'Method of shared intervention via a single data provider among shared caches for SMP bus'1999 5,943,686'Multiple cache directories for non-arbitration concurrent accessing of a cache memory'1999 5,940,611'Method and system for front-end gathering of store instructions within a data-processing system'1999 5,940,864'Shared memory-access priorization method for multiprocessors using caches and snoop responses'1999 5,940,856'Cache intervention from only one of many cache lines sharing an unmodified value'1999 5,937,172'Apparatus and method of layering cache and architectural specific functions to permit generic interface definition'1999 5,935,234'Method and system for controlling access to a shared resource in a data processing system utilizing pseudo-random priorities'1999 5,931,924'Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two pseudo-random priority weights'1999 5,924,121'Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles'1999 5,924,118'Method and system for speculatively sourcing cache memory data prior to upstream cache invalidation within a multiprocessor data-processing system'1999 5,913,231'Method and system for high speed memory address forwarding mechanism'1999 5,909,561'Apparatus and method for separately layering cache and architectural specific functions in different operational controllers to facilitate design extension'1999 5,909,698'Cache block store instruction operations where cache coherency is achieved without writing all the way back to main memory'1999 5,896,539'Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determined weighted pseudo-random priorities'1999 5,895,495'Demand-based larx-reserve protocol for SMP system buses'1999 5,895,484'Method and system for speculatively accessing cache memory data within a multiprocessor data-processing system using a cache controller'1999 5,894,569'Method and system for back-end gathering of store instructions within a data-processing system'1999 5,893,163'Method and system for allocating data among cache memories within a symmetric multiprocessor data-processing system'1999 5,883,904'Method for recoverability via redundant cache arrays'1999 5,867,511'Method for high-speed recoverable directory access'1999 5,860,101'Scalable symmetric multiprocessor data-processing system with data allocation among private caches and segments of system memory'1999 5,796,979'Data processing system having demand based write through cache with enforced ordering'1998 5,623,694'Aborting an I/O operation started before all system data is received by the I/O controller after detecting a remote retry operation'1997 5,548,797'Digital clock pulse positioning circuit for delaying a signal input by a fist time duration and a second time duration to provide a positioned clock signal'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2021Patents assigned to IBM (243)· patent assignee history

1996–2017Based in Pflugerville, TX, US· patent location history

2004–2021Based in Austin, TX, US· patent location history

2013–2014Patents assigned to DODSON JOHN S (6)· patent assignee history

2013–2017Patents assigned to GOODMAN BENJIMAN L (6)· patent assignee history

2013–2017Patents assigned to STUECHELI JEFFREY A (5)· patent assignee history

2013–2017Patents assigned to BRITTAIN MARK A (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	243	1996–2021
DODSON JOHN Sself	6	2013–2014
GOODMAN BENJIMAN L	6	2013–2017
STUECHELI JEFFREY A	5	2013–2017
BRITTAIN MARK A	3	2013–2017

Locations

Location	Patents	Span
Pflugerville, Texas, US	210	1996–2017
Austin, Texas, US	33	2004–2021