Inventor
Robert S. Blackmore
Inventor
Poughkeepsie, NY, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing81%
H04LTransmission of digital information, e.g. telegraphic communication17%
B60RVehicles, vehicle fittings, or vehicle parts, not otherwise provided for2%
PatentTitleYear
8,484,307'Host fabric interface (HFI) to perform global shared memory (GSM) operations'20138,356,151'Reporting of partially performed memory move'20138,327,101'Cache management during asynchronous memory move operations'20128,275,947'Mechanism to prevent illegal access to task address space by unauthorized tasks'20128,275,963'Asynchronous memory move across physical nodes with dual-sided communication'20128,255,913'Notification to task of completion of GSM operations by initiator node'20128,245,004'Mechanisms for communicating with an asynchronous memory mover to perform AMM operations'20128,239,879'Notification by task of completion of GSM operations at target node'20128,214,604'Mechanisms to order global shared memory operations'20128,214,424'User level message broadcast mechanism in distributed computing environment'20128,200,910'Generating and issuing global shared memory operations via a send FIFO'20128,146,094'Guaranteeing delivery of multi-packet GSM messages'20128,116,210'System and program product to recover from node failure/recovery incidents in distributed systems in which notification does not occur'20128,117,615'Facilitating intra-node data transfer in collective communications, and methods therefor'20128,095,758'Fully asynchronous memory mover'20128,023,417'Failover mechanisms in RDMA operations'20118,015,380'Launching multiple concurrent memory moves via a fully asynchronoous memory mover'20117,996,593'Interrupt handling using simultaneous multi-threading'20117,991,981'Completion of asynchronous memory move in the presence of a barrier operation'20117,966,454'Issuing global shared memory operations via direct cache injection to a host fabric interface'20117,958,327'Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture'20117,941,627'Specialized memory move barrier operations'20117,937,570'Termination of in-flight asynchronous memory move'20117,930,504'Handling of address conflicts during asynchronous memory move operations'20117,925,842'Allocating a global shared memory'20117,921,261'Reserving a global address space'20117,921,275'Method for enabling direct prefetching of data during asychronous memory move operation'20117,877,436'Mechanism to provide reliability through packet drop detection'20117,873,879'Mechanism to perform debugging of global shared memory (GSM) operations'20117,813,369'Half RDMA and half FIFO operations'20107,797,588'Mechanism to provide software guaranteed reliability for GSM operations'20107,689,992'Sharing lock mechanism between protocol layers'20107,539,989'Facilitating intra-node data transfer in collective communications'20097,536,468'Interface method, system, and program product for facilitating layering of a data communications protocol over an active message layer protocol'20097,493,436'Interrupt handling using simultaneous multi-threading'20097,480,298'Lazy deregistration of user virtual machine to adapter protocol virtual offsets'20097,454,491'Method and system for efficiently transferring a self-defined non-contiguous message in a one-sided communication model'20087,430,615'RDMA server (OSI) global TCE tables'20087,379,444'Method to recover from node failure/recovery incidents in distributed systems in which notification does not occur'20087,231,638'Memory sharing in a distributed data processing system using modified address space to create extended address space for copying data'20077,089,289'Mechanisms for efficient message passing with copy avoidance in a distributed system using advanced network devices'20066,799,200'Mechanisms for efficient message passing with copy avoidance in a distributed system'20046,782,464'Mapping a logical address to a plurality on non-logical addresses'20046,782,537'Establishing a communicator across multiple processes in a multithreaded computing environment'20046,735,620'Efficient protocol for retransmit logic in reliable zero copy message transport'20046,389,478'Efficient non-contiguous I/O vector and strided data transfer in one sided communication on multiprocessor computers'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2013Patents assigned to IBM (46)· patent assignee history
2002–2013Based in Poughkeepsie, NY, US· patent location history
2012–2013Patents assigned to BLACKMORE ROBERT S (15)· patent assignee history
2012–2013Patents assigned to KIM CHULHO (11)· patent assignee history
2012–2013Patents assigned to XUE HANHONG (10)· patent assignee history
2012–2013Patents assigned to ARIMILLI LAKSHMINARAYANA B (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 46 | 2002–2013 |
| BLACKMORE ROBERT Sself | 15 | 2012–2013 |
| KIM CHULHO | 11 | 2012–2013 |
| XUE HANHONG | 10 | 2012–2013 |
| ARIMILLI LAKSHMINARAYANA B | 7 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 46 | 2002–2013 |