Inventor
Rebecca D. Mih
Inventor
Wappingers Falls, NY, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices21%
H10DInorganic electric semiconductor devices13%
H10BElectronic memory devices8%
G11CStatic stores3%
H01JElectric discharge tubes or discharge lamps3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
8,815,475'Reticle carrier'20148,439,728'Reticle carrier'20138,110,321'Method of manufacture of damascene reticle'20126,727,589'Dual damascene flowable oxide insulation structure and metallic barrier'20046,504,207'Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same'20036,479,884'Interim oxidation of silsesquioxane dielectric for dual damascene process'20026,448,629'Semiconductor device and method of making same'20026,429,522'Microprocessor having air as a dielectric and encapsulated lines'20026,429,067'Dual mask process for semiconductor devices'20026,407,396'Wafer metrology structure'20026,391,703'Buried strap for DRAM using junction isolation technique'20026,348,736'In situ formation of protective layer on silsesquioxane dielectric for dual damascene process'20026,329,280'Interim oxidation of silsesquioxane dielectric for dual damascene process'20016,326,275'DRAM cell with vertical CMOS transistor'20016,284,574'Method of producing heat dissipating structure for semiconductor devices'20016,268,261'Microprocessor having air as a dielectric and encapsulated lines and process for manufacture'20016,258,732'Method of forming a patterned organic dielectric layer on a substrate'20016,228,745'Selective reduction of sidewall slope on isolation edge'20016,221,780'Dual damascene flowable oxide insulation structure and metallic barrier'20016,132,940'Method for producing constant profile sidewalls'20006,114,096'Asymmetrical resist sidewall'20006,015,991'Asymmetrical field effect transistor'20005,985,492'Multi-phase mask'19995,948,571'Asymmetrical resist sidewall'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2014Patents assigned to IBM (24)· patent assignee history
1999–2004Based in Wappingers Falls, NY, US· patent location history
2012–2013Patents assigned to CANAPERI DONALD F (2)· patent assignee history
2012–2013Patents assigned to GRABARZ HENRY (2)· patent assignee history
2012–2013Patents assigned to HIBBS MICHAEL S (2)· patent assignee history
2012–2013Patents assigned to KRISHNAN MAHADEVAIYER (2)· patent assignee history
2012–2014Based in Los Gatos, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 24 | 1999–2014 |
| CANAPERI DONALD F | 2 | 2012–2013 |
| GRABARZ HENRY | 2 | 2012–2013 |
| HIBBS MICHAEL S | 2 | 2012–2013 |
| KRISHNAN MAHADEVAIYER | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wappingers Falls, New York, US | 21 | 1999–2004 |
| Los Gatos, California, US | 3 | 2012–2014 |