Inventor

Kushagra Vaid

Inventor
San Jose, CA, US

Overview

37→
Patents
2000–2020
Patent span
Physics
Primary field (CPC G)

Patents· 37 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing77%
G11CStatic stores6%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%
H02JElectric power networks2%
H04LTransmission of digital information, e.g. telegraphic communication2%
Y04SSystems integrating technologies related to power network operation, communication or information technologies for improving the electrical power generation, transmission, distribution, management or usage, i.e. smart grids2%
PatentTitleYear
10,664,166Application-transparent hybridized caching for high-performance storage20209,779,249'Launching a secure kernel in a multiprocessor system'20179,507,952'Launching a secure kernel in a multiprocessor system'20169,436,517'Reliability-aware application scheduling'20169,213,865'Launching a secure kernel in a multiprocessor system'20159,110,783'Application-transparent hybridized caching for high-performance storage'20158,984,265'Server active management technology (AMT) assisted secure boot'20158,874,906'Launching a secure kernel in a multiprocessor system'20148,645,959'Method and apparatus for communication between two or more processing elements'20148,533,514'Power-capping based on UPS capacity'20138,464,048'Launching a secure kernel in a multiprocessor system'20138,458,412'Transaction based shared data operations in a multiprocessor environment'20138,321,630'Application-transparent hybridized caching for high-performance storage'20128,261,266'Deploying a virtual machine having a virtual hardware configuration matching an improved hardware profile with respect to execution of an application'20128,250,364'Launching a secure kernel in a multiprocessor system'20128,214,830'Performance in a virtualization architecture with a processor abstraction layer'20128,176,266'Transaction based shared data operations in a multiprocessor environment'20128,161,280'Launching a secure kernel in a multiprocessor system'20128,135,723'Leveraging low-latency memory access'20127,984,248'Transaction based shared data operations in a multiprocessor environment'20117,849,327'Technique to virtualize processor input/output resources'20107,774,600'Launching a secure kernel in a multiprocessor system'20107,770,005'Launching a secure kernel in a multiprocessor system'20107,757,081'Launching a secure kernel in a multiprocessor system'20107,747,846'Managed redundant enterprise basic input/output system store update'20107,725,713'Launching a secure kernel in a multiprocessor system'20107,721,148'Method and apparatus for redirection of machine check interrupts in multithreaded systems'20107,698,552'Launching a secure kernel in a multiprocessor system'20107,587,639'System and method for error injection using a flexible program interface field'20097,426,648'Global and pseudo power state management for multiple processing elements'20087,360,103'P-state feedback to operating system with hardware coordination'20087,353,433'Poisoned error signaling for proactive OS recovery'20087,254,676'Processor cache memory as RAM for execution of boot code'20077,213,129'Method and system for a two stage pipelined instruction decode and alignment using previous instruction length'20076,684,322'Method and system for instruction length decode'20046,598,154'Precoding branch instructions to reduce branch-penalty in pipelined processors'20036,112,295'High frequency pipeline decoupling queue with non-overlapping read and write signals within a single clock cycle'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2017Patents assigned to INTEL CORP (29)· patent assignee history
2000–2007Based in Sunnyvale, CA, US· patent location history
2007–2017Based in San Jose, CA, US· patent location history
2010–2012Patents assigned to VAID KUSHAGRA V (4)· patent assignee history
2012–2015Patents assigned to VAID KUSHAGRA (10)· patent assignee history
2012–2016Patents assigned to MICROSOFT CORP (5)· patent assignee history
2012–2013Patents assigned to GRAWROCK DAVID W (3)· patent assignee history
2012–2020Based in Sammamish, WA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP292000–2017
VAID KUSHAGRAself102012–2015
MICROSOFT CORP52012–2016
VAID KUSHAGRA Vself42010–2012
GRAWROCK DAVID W32012–2013
Locations
LocationPatentsSpan
San Jose, California, US262007–2017
Sammamish, Washington, US72012–2020
Sunnyvale, California, US42000–2007