Inventor
Hsin-Jung Lo
Inventor
Taipei, TW
Overview
Patents· 30 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1063%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation7%
G06FElectric digital data processing5%
G11CStatic stores5%
H01LSemiconductor devices5%
G02BOptical elements, systems or apparatus2%
H05KPrinted circuits2%
PatentTitleYear
9,612,615'Integrated circuit chip using top post-passivation technology and bottom structure technology'20178,837,872'Waveguide structures for signal and/or power transmission in a semiconductor device'20148,836,146'Chip package and method for fabricating the same'20148,692,374'Carbon nanotube circuit component structure'20148,456,856'Integrated circuit chip using top post-passivation technology and bottom structure technology'20138,426,958'Stacked chip package with redistribution lines'20138,399,989'Metal pad or metal bump over pad exposed by passivation layer'20138,368,193'Chip package'20138,344,524'Wire bonding method for preventing polymer cracking'20138,319,354'Semiconductor chip with post-passivation scheme formed over passivation layer'20128,304,766'Semiconductor chip with a bonding pad having contact and test areas'20128,232,192'Process of bonding circuitry components'20128,193,636'Chip assembly with interconnection by metal bump'20128,159,074'Chip structure'20128,148,822'Bonding pad on IC substrate and method for making the same'20128,044,475'Chip package'20118,004,092'Semiconductor chip with post-passivation scheme formed over passivation layer'20117,990,037'Carbon nanotube circuit component structure'20117,973,401'Stacked chip package with redistribution lines'20117,964,973'Chip structure'20117,964,961'Chip package'20117,960,269'Method for forming a double embossing structure'20117,947,978'Semiconductor chip with bond area'20117,932,172'Semiconductor chip and process for forming the same'20117,508,059'Stacked chip package with redistribution lines'20097,495,304'Chip package'20097,473,999'Semiconductor chip and process for forming the same'20097,462,558'Method for fabricating a circuit component'20087,452,803'Method for fabricating chip structure'20087,397,121'Semiconductor chip with post-passivation scheme formed over passivation layer'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2017Patents assigned to MEGICA CORP (27)· patent assignee history
2008–2017Based in Taipei, TW· patent location history
2008–2014Based in Jhonghe, TW· patent location history
2009–2013Based in Yonghe City, TW· patent location history
2009Based in Hsinchu, TW· patent location history
2012–2014Patents assigned to LO HSIN-JUNG (14)· patent assignee history
2012–2014Patents assigned to LIN MOU-SHIUNG (11)· patent assignee history
2012–2014Patents assigned to CHOU CHIU-MING (8)· patent assignee history
2012–2014Patents assigned to CHOU CHIEN-KANG (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MEGICA CORP | 27 | 2008–2017 |
| LO HSIN-JUNGself | 14 | 2012–2014 |
| LIN MOU-SHIUNG | 11 | 2012–2014 |
| CHOU CHIU-MING | 8 | 2012–2014 |
| CHOU CHIEN-KANG | 6 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 22 | 2008–2017 |
| Yonghe City, TW | 4 | 2009–2013 |
| Jhonghe, TW | 3 | 2008–2014 |
| Hsinchu, TW | 1 | 2009 |