Inventor
Darrell G. Hill
Inventor
Plano, TX, US
Overview
Patents· 58 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices32%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H01LSemiconductor devices13%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H03FAmplifiers4%
A61GTransport, personal conveyances, or accommodation specially adapted for patients or disabled persons1%
B82YSpecific uses or applications of nanostructures1%
H04BTransmission1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
10,879,168Transistor with non-circular via connections in two orientations202010,825,924Semiconductor device with selectively etched surface passivation202010,741,496Semiconductor devices with a protection layer and methods of fabrication202010,629,526Transistor with non-circular via connections in two orientations202010,594,276Multi-path amplifier circuit or system and methods of implementation thereof202010,541,324Semiconductor device with a recessed ohmic contact and methods of fabrication202010,522,670Semiconductor device with selectively etched surface passivation201910,438,940ESD protection for depletion-mode devices201910,128,364Semiconductor devices with an enhanced resistivity region and methods of fabrication therefor201810,074,588Semiconductor devices with a thermally conductive layer and methods of their fabrication20189,905,658'Transistors with field plates resistant to field plate material migration and methods of their fabrication'20189,799,760'Semiconductor device with selectively etched surface passivation'20179,779,988'Semiconductor devices with inner via'20179,685,345'Semiconductor devices with integrated Schottky diodes and methods of fabrication'20179,614,046'Semiconductor devices with a thermally conductive layer'20179,362,198'Semiconductor devices with a thermally conductive layer and methods of their fabrication'20169,153,448'Semiconductor device with selectively etched surface passivation'20159,111,868'Semiconductor device with selectively etched surface passivation'20158,946,776'Semiconductor device with selectively etched surface passivation'20158,609,538'Methods relating to the fabrication of devices having conductive substrate vias with catch-pad etch-stops'20138,410,580'Device having conductive substrate via with catch-pad etch-stop'20138,160,518'Multi-mode transceiver having tunable harmonic termination circuit and method therefor'20127,849,540'Reusable surgical perioperative positioning system'20107,723,224'Microelectronic assembly with back side metallization and method for forming the same'20107,642,182'ESD protection for passive integrated devices'20107,335,955'ESD protection for passive integrated devices'20086,924,697'Semiconductor device and method thereof'20056,919,590'Heterojunction bipolar transistor with monolithically integrated junction field effect transistor and method of manufacturing same'20056,855,965'Method of manufacturing a semiconductor component and semiconductor component thereof'20056,825,727'Radio frequency power transistor avalanche breakdown detection circuit and method therefor'20046,823,870'Patient safety straps'20046,798,064'Electronic component and method of manufacture'20046,621,351'RF amplifier and method therefor'20036,465,297'Method of manufacturing a semiconductor component having a capacitor'20026,368,929'Method of manufacturing a semiconductor component and semiconductor component thereof'20026,159,816'Method of fabricating a bipolar transistor'20006,028,348'Low thermal impedance integrated circuit'20006,025,615'Microwave heterojunction bipolar transistors with emitters designed for high power applications and method for fabricating same'20006,023,336'Technique for automated alignment of semiconductor chips'20005,789,301'Method for reducing extrinsic base-collector capacitance'19985,783,966'Reducing junction capacitance and increasing current gain in collector-up bipolar transistors'19985,710,068'Low thermal impedance integrated circuit'19985,702,958'Method for the fabrication of bipolar transistors'19975,700,701'Method for reducing junction capacitance and increasing current gain in collector-up bipolar transistors'19975,552,617'Bipolar transistor'19965,525,817'Bipolar transistor'19965,525,818'Reducing extrinsic base-collector capacitance'19965,515,562'Sacral and perineal pads'19965,445,976'Method for producing bipolar transistor having reduced base-collector capacitance'19955,434,091'Method for making collector up bipolar transistors having reducing junction capacitance and increasing current gain'19955,391,504'Method for producing integrated quasi-complementary bipolar transistors and field effect transistors'19955,389,554'Method for fabricating microwave heterojunction bipolar transistors with emitters designed for high power applications'19955,330,932'Method for fabricating GaInP/GaAs structures'19945,298,438'Method of reducing extrinsic base-collector capacitance in bipolar transistors'19945,298,453'Integration of epitaxial structures'19945,286,997'Method for forming an isolated, low resistance epitaxial subcollector for bipolar transistors'19945,278,083'Method for making reliable connections to small features of integrated circuits'19945,171,697'Method of forming multiple layer collector structure for bipolar transistors'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2000Patents assigned to TEXAS INSTRUMENTS INC (20)· patent assignee history
1992–2000Based in Plano, TX, US· patent location history
1996–2004Based in Edina, MN, US· patent location history
2002–2017Based in Tempe, AZ, US· patent location history
2004–2018Patents assigned to FREESCALE SEMICONDUCTOR INC (16)· patent assignee history
2010Based in Palm Desert, CA, US· patent location history
2012–2018Patents assigned to HILL DARRELL G (10)· patent assignee history
2013–2017Patents assigned to GREEN BRUCE M (7)· patent assignee history
2015–2020Based in Chandler, AZ, US· patent location history
2017–2020Patents assigned to NXP USA INC (15)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 20 | 1992–2000 |
| FREESCALE SEMICONDUCTOR INC | 16 | 2004–2018 |
| NXP USA INC | 15 | 2017–2020 |
| HILL DARRELL Gself | 10 | 2012–2018 |
| GREEN BRUCE M | 7 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Plano, Texas, US | 22 | 1992–2000 |
| Tempe, AZ, US | 18 | 2002–2017 |
| Chandler, AZ, US | 15 | 2015–2020 |
| Edina, Minnesota, US | 2 | 1996–2004 |
| Palm Desert, California, US | 1 | 2010 |