Inventor
Keith A. Joyner
Inventor
Richardson, TX, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1034%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1030%
H10DInorganic electric semiconductor devices20%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
B82YSpecific uses or applications of nanostructures3%
C23CCoating metallic material2%
C25FProcesses for the electrolytic removal of materials from objects2%
H01JElectric discharge tubes or discharge lamps2%
PatentTitleYear
7,459,734'Method for manufacturing and structure for transistors with reduced gate to contact spacing'20087,339,214'Methods and apparatus for inducing stress in a semiconductor device'20087,101,772'Means for forming SOI'20066,806,151'Methods and apparatus for inducing stress in a semiconductor device'20046,767,777'Method for manufacturing and structure for transistors with reduced gate to contact spacing including etching to thin the spacers'20046,737,347'Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device'20046,376,859'Variable porosity porous silicon isolation'20026,376,285'Annealed porous silicon with epitaxial layer for SOI'20026,228,747'Organic sidewall spacers used with resist'20016,214,699'Method for forming an isolation structure in a substrate'20016,207,511'Self-aligned trenched-channel lateral-current-flow transistor'20016,180,491'Isolation structure and method'20016,171,969'Uniform dopant distribution for mesas of semiconductors'20016,118,161'Self-aligned trenched-channel lateral-current-flow transistor'20006,114,741'Trench isolation of a CMOS structure'20006,057,214'Silicon-on-insulation trench isolation structure and method for forming'20006,004,871'Implant enhancement of titanium silicidation'19995,982,006'Active silicon-on-insulator region having a buried insulation layer with tapered edge'19995,909,628'Reducing non-uniformity in a refill layer thickness for a semiconductor device'19995,882,981'Mesa isolation Refill Process for Silicon on Insulator Technology Using Flowage Oxides as the Refill Material'19995,863,827'Oxide deglaze before sidewall oxidation of mesa or trench'19995,548,149'Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate'19965,440,132'Systems and methods for controlling the temperature and uniformity of a wafer during a SIMOX implantation process'19955,429,955'Method for constructing semiconductor-on-insulator'19955,364,800'Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate'19945,352,341'Reducing leakage current in silicon-on-insulator substrates'19944,507,851'Process for forming an electrical interconnection system on a semiconductor'1985Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1985–2008Patents assigned to TEXAS INSTRUMENTS INC (27)· patent assignee history
1985–2008Based in Richardson, TX, US· patent location history
1999–2008Based in Dallas, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 27 | 1985–2008 |
Locations
| Location | Patents | Span |
|---|---|---|
| Richardson, Texas, US | 24 | 1985–2008 |
| Dallas, Texas, US | 3 | 1999–2008 |