Inventor
Miguel Comparan
Inventor
Rochester, MN, US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing39%
G06TImage data processing or generation, in general16%
G02BOptical elements, systems or apparatus11%
G09GArrangements or circuits for control of indicating devices using static means to present variable information10%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
G03HHolographic processes or apparatus4%
H04NPictorial communication, e.g. television4%
A61MDevices for introducing media into, or onto, the body1%
A63FCard, board, or roulette games1%
G01RMeasuring electric variables1%
PatentTitleYear
10,831,504Processor with hybrid pipeline capable of operating in out-of-order and in-order modes202010,672,368No miss cache structure for real-time image transformations with multiple LSR processing engines202010,514,753Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection power201910,410,349Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection power201910,403,029Methods and systems for multistage post-rendering image transformation201910,360,832Post-rendering image transformation using parallel image transformation pipelines201910,338,816Reducing negative effects of insufficient data throughput for real-time processing201910,255,891No miss cache structure for real-time image transformations with multiple LSR processing engines201910,241,470No miss cache structure for real-time image transformations with data compression201910,242,654No miss cache structure for real-time image transformations201910,114,652Processor with hybrid pipeline capable of operating in out-of-order and in-order modes201810,095,408Reducing negative effects of insufficient data throughput for real-time processing20189,978,118No miss cache structure for real-time image transformations with data compression20189,354,884'Processor with hybrid pipeline capable of operating in out-of-order and in-order modes'20169,092,347'Allocating cache for use as a dedicated local storage'20159,053,037'Allocating cache for use as a dedicated local storage'20159,021,237'Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread'20158,954,973'Transferring architected state between cores'20158,949,836'Transferring architected state between cores'20158,856,602'Multi-core processor with internal voting-based built in self test (BIST)'20148,719,508'Near neighbor data cache sharing'20148,719,507'Near neighbor data cache sharing'20148,560,897'Hard memory array failure recovery utilizing locking structure'20138,493,398'Dynamic data type aligned cache optimized for misaligned packed structures'20138,392,664'Network on chip'20138,310,497'Anisotropic texture filtering with texture data prefetching'20128,217,953'Anisotropic texture filtering with texture data prefetching'20128,082,420'Method and apparatus for executing instructions'20118,010,750'Network on chip that maintains cache coherency with invalidate commands'20117,917,703'Network on chip that maintains cache coherency with invalidate commands'20117,890,699'Processing unit incorporating L1 cache bypass'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2020Patents assigned to IBM (20)· patent assignee history
2011–2015Patents assigned to COMPARAN MIGUEL (11)· patent assignee history
2011–2015Based in Rochester, MN, US· patent location history
2013–2015Patents assigned to SHEARER ROBERT A (6)· patent assignee history
2013–2015Patents assigned to HOOVER RUSSELL D (4)· patent assignee history
2016–2020Based in Kirkland, WA, US· patent location history
2018–2020Patents assigned to MICROSOFT TECHNOLOGY LICENSING LLC (11)· patent assignee history
2018–2020Based in Kenmore, WA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 20 | 2011–2020 |
| COMPARAN MIGUELself | 11 | 2011–2015 |
| MICROSOFT TECHNOLOGY LICENSING LLC | 11 | 2018–2020 |
| SHEARER ROBERT A | 6 | 2013–2015 |
| HOOVER RUSSELL D | 4 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Rochester, Minnesota, US | 17 | 2011–2015 |
| Kenmore, Washington, US | 11 | 2018–2020 |
| Kirkland, Washington, US | 3 | 2016–2020 |