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Inventor

Shai Rotem

Inventor
Haifa, IL

Overview

25→
Patents
1993–2021
Patent span
General tagging of new technological developments
Primary field (CPC Y)

Patents· 25 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing31%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use16%
G11CStatic stores12%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications12%
Y02PClimate change mitigation technologies in the production or processing of goods12%
Y10TTechnical subjects covered by former us classification8%
H03KPulse technique5%
G01RMeasuring electric variables4%
PatentTitleYear
10,955,885Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain202110,536,139Charge-saving power-gate apparatus and method202010,228,738Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain20199,966,940Charge-saving power-gate apparatus and method20189,874,925Method and apparatus for a zero voltage processor sleep state20189,870,044'Method and apparatus for a zero voltage processor sleep state'20189,841,807'Method and apparatus for a zero voltage processor sleep state'20179,235,258'Method and apparatus for a zero voltage processor'20169,223,390'Method and apparatus for a zero voltage processor'20159,223,389'Method and apparatus for a zero voltage processor'20159,141,180'Method and apparatus for a zero voltage processor sleep state'20158,707,062'Method and apparatus for powered off processor core mode'20147,664,970'Method and apparatus for a zero voltage processor sleep state'20107,523,327'System and method of coherent data transfer during processor idle states'20097,233,162'Arrangements having IC voltage and thermal resistance designated on a per IC basis'20077,112,979'Testing arrangement to distribute integrated circuits'20067,109,737'Arrangements having IC voltage and thermal resistance designated on a per IC basis'20066,314,553'Circuit synthesis and verification using relative timing'20015,978,899'Apparatus and method for parallel processing and self-timed serial marking of variable length instructions'19995,948,096'Apparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytes'19995,941,982'Efficient self-timed marking of lengthy variable length instructions'19995,931,944'Branch instruction handling in a self-timed marking system'19995,574,872'Method and apparatus for controlling the saving of pipelines in pipelined processors during trap handling'19965,465,216'Automatic design verification'19955,265,227'Parallel protection checking in an address translation look-aside buffer'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2021Patents assigned to INTEL CORP (25)· patent assignee history
1993Based in Hoffit, IL· patent location history
1995–2007Based in Hofit, IL· patent location history
1999Based in Beaverton, OR, US· patent location history
2009–2021Based in Haifa, IL· patent location history
2014–2019Patents assigned to ROTEM SHAI (3)· patent assignee history
2014Patents assigned to CONRAD JOHN B (1)· patent assignee history
2018–2019Patents assigned to UNGER NORBERT (2)· patent assignee history
2018–2019Patents assigned to ZELIKSON MICHAEL (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP251993–2021
ROTEM SHAIself32014–2019
UNGER NORBERT22018–2019
ZELIKSON MICHAEL22018–2019
CONRAD JOHN B12014
Locations
LocationPatentsSpan
Haifa, IL142009–2021
Hofit, IL61995–2007
Beaverton, OR, US41999
Hoffit, IL11993