Inventor
Hisakazu Otoi
Inventor
Yokkaichi, JP
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices30%
H01LSemiconductor devices23%
H10DInorganic electric semiconductor devices21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H10NElectric solid-state devices not otherwise provided for3%
B82YSpecific uses or applications of nanostructures2%
PatentTitleYear
10,985,176Three-dimensional memory device containing eye-shaped contact via structures located in laterally-undulating trenches and method of making the same202110,892,267Three-dimensional memory device containing through-memory-level contact via structures and method of making the same202110,879,262Three-dimensional memory device containing eye-shaped contact via structures located in laterally-undulating trenches and method of making the same202010,707,314Surround gate vertical field effect transistors including tubular and strip electrodes and method of making the same202010,629,611Three-dimensional memory device and methods of making the same using replacement drain select gate electrodes202010,615,172Three-dimensional memory device having double-width staircase regions and methods of manufacturing the same202010,586,803Three-dimensional memory device and methods of making the same using replacement drain select gate electrodes202010,516,025Three-dimensional NAND memory containing dual protrusion charge trapping regions and methods of manufacturing the same201910,490,564Three-dimensional memory device and methods of making the same using replacement drain select gate electrodes201910,490,569Three-dimensional memory device and method of making the same using concurrent formation of memory openings and contact openings201910,354,987Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same201910,354,980Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same201910,347,654Three-dimensional memory device employing discrete backside openings and methods of making the same201910,115,895Vertical field effect transisitors having a rectangular surround gate and method of making the same20188,669,172'Method of manufacturing nonvolatile semiconductor device'20148,211,777'Method of manufacturing nonvolatile semiconductor device'20127,705,392'Nonvolatile semiconductor device and method of manufacturing nonvolatile semiconductor device'20106,930,351'Semiconductor device with dummy gate electrode'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2010Patents assigned to RENESAS TECH CORP (2)· patent assignee history
2005Based in Hyogo, JP· patent location history
2010–2014Based in Tokyo, JP· patent location history
2012–2014Patents assigned to NISHIDA AKIO (2)· patent assignee history
2012–2014Patents assigned to OTOI HISAKAZU (2)· patent assignee history
2012–2014Patents assigned to RENESAS ELECTRONICS CORP (2)· patent assignee history
2018–2021Patents assigned to SANDISK TECHNOLOGIES LLC (14)· patent assignee history
2018–2021Based in Yokkaichi, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 14 | 2018–2021 |
| NISHIDA AKIO | 2 | 2012–2014 |
| OTOI HISAKAZUself | 2 | 2012–2014 |
| RENESAS ELECTRONICS CORP | 2 | 2012–2014 |
| RENESAS TECH CORP | 2 | 2005–2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yokkaichi, JP | 14 | 2018–2021 |
| Tokyo, JP | 3 | 2010–2014 |
| Hyogo, JP | 1 | 2005 |