Inventor
Sharad Kumar Gupta
Inventor
Bangalore, IN
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores60%
G06FElectric digital data processing23%
H04NPictorial communication, e.g. television5%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
H03KPulse technique3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H04WWireless communication networks3%
LOC093%
PatentTitleYear
11,049,552Write assist circuitry for memory202111,043,271Reusing a cell block for hybrid dual write202111,037,627Cell block allocation for hybrid dual write202110,867,668Area efficient write data path circuit for SRAM yield enhancement202010,811,088Access assist with wordline adjustment with tracking cell202010,811,086SRAM write yield enhancement with pull-up strength modulation202010,732,838Logical grouping for hybrid dual write202010,560,698Graphics server and method for streaming rendered content via a remote graphics processing service202010,446,196Flexible power sequencing for dual-power memory201910,154,265Graphics server and method for streaming rendered content via a remote graphics processing service201810,140,224Noise immune data path scheme for multi-bank memory architecture20189,952,148Non-invasive optical characterization of biomaterial mineralization20189,947,419Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits20189,928,889'Bitline precharge control and tracking scheme providing increased memory cycle speed for pseudo-dual-port memories'20189,928,898'Wordline adjustment scheme'20189,875,790Boost charge recycle for low-power memory20189,875,776Bit writability implementation for memories20189,865,316'Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power'20189,837,144Apparatus and method for controlling boost capacitance for low power memory circuits20179,721,650'Architecture to improve write-ability in SRAM'20179,607,674'Pulse latch reset tracking at high differential voltage'20179,565,183'Location and device based student access control'20179,218,892'Error prediction in logic and memory devices'20158,762,804'Error prediction in logic and memory devices'20148,320,210'Memory circuit and a tracking circuit thereof'20127,940,541'Bit cell designs for ternary content addressable memory'20117,894,226'Content addressable memory based on a ripple search scheme'20117,804,699'Segmented ternary content addressable memory search architecture'2010D0540665'Pharmaceutical package'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2015Patents assigned to TEXAS INSTRUMENTS INC (6)· patent assignee history
2010–2012Based in Kanpur, IN· patent location history
2011Based in Uttar Pradesh, IN· patent location history
2012–2018Patents assigned to GUPTA SHARAD (3)· patent assignee history
2014–2021Based in Bangalore, IN· patent location history
2017–2021Patents assigned to QUALCOMM INC (15)· patent assignee history
2018–2020Patents assigned to NVIDIA CORP (2)· patent assignee history
2018Based in Medford, MA, US· patent location history
2019Based in Bagalore, IN· patent location history
2020–2021Patents assigned to WESTERN DIGITAL TECH INC (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 15 | 2017–2021 |
| TEXAS INSTRUMENTS INC | 6 | 2010–2015 |
| GUPTA SHARADself | 3 | 2012–2018 |
| WESTERN DIGITAL TECH INC | 3 | 2020–2021 |
| NVIDIA CORP | 2 | 2018–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bangalore, IN | 21 | 2014–2021 |
| Kanpur, IN | 2 | 2010–2012 |
| Uttar Pradesh, IN | 2 | 2011 |
| Bagalore, IN | 1 | 2019 |
| Medford, Massachusetts, US | 1 | 2018 |