Inventor
Brian Roberds
Inventor
Santa Clara, CA, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
Y10TTechnical subjects covered by former us classification5%
A61BDiagnosis2%
B82YSpecific uses or applications of nanostructures2%
C04BLime, magnesia2%
PatentTitleYear
7,615,465'Creation of high mobility channels in thin-body SOI devices'20097,485,541'Creation of high mobility channels in thin-body SOI devices'20097,067,386'Creation of high mobility channels in thin-body SOI devices'20066,952,040'Transistor structure and method of fabrication'20056,908,832'In situ plasma wafer bonding method'20056,873,013'Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering'20056,815,310'Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel'20046,809,017'Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication'20046,740,913'MOS transistor using mechanical stress to control short channel effects'20046,717,213'Creation of high mobility channels in thin-body SOI devices'20046,656,822'Method for reduced capacitance interconnect system using gaseous implants into the ILD'20036,653,700'Transistor structure and method of fabrication'20036,645,828'In situ plasma wafer bonding method'20036,642,133'Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering'20036,638,835'Method for bonding and debonding films using a high-temperature polymer'20036,620,713'Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication'20036,605,498'Semiconductor transistor having a backfilled channel material'20036,563,152'Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel'20036,518,109'Technique to produce isolated junctions by forming an insulation layer'20036,489,655'Integrated circuit with dynamic threshold voltage'20026,399,973'Technique to produce isolated junctions by forming an insulation layer'20026,362,078'Dynamic threshold voltage device and methods for fabricating dynamic threshold voltage devices'20026,362,082'Methodology for control of short channel effects in MOS transistors'20026,300,221'Method of fabricating nanoscale structures'20016,281,532'Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering'20016,261,878'Integrated circuit with dynamic threshold voltage'20016,228,694'Method of increasing the mobility of MOS transistors by use of localized stress regions'20016,180,496'In situ plasma wafer bonding method'20015,503,704'Nitrogen based low temperature direct bonding'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996Patents assigned to UNIV CALIFORNIA (1)· patent assignee history
1996Based in West Sacramento, CA, US· patent location history
2001–2009Patents assigned to INTEL CORP (25)· patent assignee history
2001–2005Patents assigned to SILICON GENESIS CORP (3)· patent assignee history
2001–2005Based in Santa Clara, CA, US· patent location history
2002–2005Based in Beaverton, OR, US· patent location history
2003–2009Based in Escondido, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 25 | 2001–2009 |
| SILICON GENESIS CORP | 3 | 2001–2005 |
| UNIV CALIFORNIA | 1 | 1996 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 12 | 2001–2005 |
| Escondido, California, US | 10 | 2003–2009 |
| Beaverton, OR, US | 6 | 2002–2005 |
| West Sacramento, California, US | 1 | 1996 |