Inventor
HONG BOK WE
Inventor
US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H01LSemiconductor devices36%
H05KPrinted circuits10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H01QAntennas, i.e. radio aerials3%
H10DInorganic electric semiconductor devices2%
G11CStatic stores1%
H10BElectronic memory devices1%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
12,581,966Electronic component placed on core of substrate202612,543,599Package comprising a first substrate, a second substrate and an electrical device coupled to a bottom surface of the second substrate202612,500,146Substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength, and related IC packages and fabrication methods202512,424,559Package with a substrate comprising embedded escape interconnects and surface escape interconnects202512,381,174Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods202512,243,855Package comprising channel interconnects located between solder interconnects202512,230,552Recess structure for padless stack via202512,100,645Integrated circuit (IC) package employing added metal for embedded metal traces in ETS-based substrate for reduced signal path impedance, and related fabrication methods202412,021,063Circular bond finger pad202411,955,409Substrate comprising interconnects in a core layer configured for skew matching202411,948,877Hybrid package apparatus and method of fabricating202411,832,391Terminal connection routing and method the same202311,823,983Package with a substrate comprising pad-on-pad interconnects202311,817,365Thermal mitigation die using back side etch202311,804,645Multi-sided antenna module employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related fabrication methods202311,791,276Package comprising passive component between substrates for improved power distribution network (PDN) performance202311,791,320Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods202311,784,151Redistribution layer connection202311,776,888Package with a substrate comprising protruding pad interconnects202311,749,579Thermal structures adapted to electronic device heights in integrated circuit (IC) packages202311,749,611Package with a substrate comprising periphery interconnects202311,715,688Variable dielectric constant materials in same layer of a package202311,682,607Package having a substrate comprising surface interconnects aligned with a surface of the substrate202311,658,391Antenna module202311,605,595Packages with local high-density routing region embedded within an insulating layer202311,594,491Multi-die interconnect202311,581,262Package comprising a die and die side redistribution layers (RDL)202311,581,251Package comprising inter-substrate gradient interconnect structure202311,562,962Package comprising a substrate and interconnect device configured for diagonal routing202311,551,939Substrate comprising interconnects embedded in a solder resist layer202311,552,015Substrate comprising a high-density interconnect portion embedded in a core layer202311,545,425Substrate comprising interconnects embedded in a solder resist layer202311,545,439Package comprising an integrated device coupled to a substrate through a cavity202311,545,435Double sided embedded trace substrate202311,502,049Package comprising multi-level vertically stacked redistribution portions202211,456,291Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die ("die") module employing stacked dice, and related fabrication methods202211,444,019Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package202211,393,808Ultra-low profile stacked RDL semiconductor package202211,342,246Multi-terminal integrated passive devices embedded on die and a method for fabricating the multi-terminal integrated passive devices202211,302,656Passive device orientation in core for improved power delivery in package202211,296,024Nested interconnect structure in concentric arrangement for improved package architecture202211,296,022Package and substrate comprising interconnects with semi-circular planar shape and/or trapezoid planar shape202211,289,453Package comprising a substrate and a high-density interconnect structure coupled to the substrate202211,258,165Asymmetric antenna structure202211,183,446X.5 layer substrate202111,177,223Electromagnetic interference shielding for packages and modules2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to QUALCOMM INC (46)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 46 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 46 | 2021–2026 |