Inventor
IAN SHAEFFER
Inventor
US
Overview
Patents· 37 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores33%
G06FElectric digital data processing32%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
H01LSemiconductor devices7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
H03MCoding5%
H03KPulse technique4%
PatentTitleYear
12,394,471Memory system topologies including a memory die stack202512,386,763Protocol including selective output by memory of a timing reference signal202512,347,479Command-triggered data clock distribution mode202512,301,227On-die termination202512,298,848Memory error detection202512,298,920Memory access during memory calibration202512,249,399On-die termination of address and command signals202512,147,367Folded memory modules202412,142,348Memory device comprising programmable command-and-address and/or data interfaces202412,136,452Method and apparatus for calibrating write timing in a memory system202412,002,540On-die termination of address and command signals202411,955,161Command-triggered data clock distribution mode202411,947,468Memory access during memory calibration202411,928,020Memory error detection202411,816,047Protocol including a command-specified timing reference signal202311,783,879Memory device comprising programmable command-and-address and/or data interfaces202311,782,863Memory module with configurable command buffer202311,755,521Folded memory modules202311,742,855On-die termination202311,727,982Memory system topologies including a memory die stack202311,688,441On-die termination of address and command signals202311,682,448Method and apparatus for calibrating write timing in a memory system202311,651,823Fractional program commands for memory devices202311,587,605Command-triggered data clock distribution202311,579,965Memory error detection202311,474,957Memory access during memory calibration202211,468,928On-die termination of address and command signals202211,409,682Folded memory modules202211,404,103Method and apparatus for calibrating write timing in a memory system202211,372,795Memory with alternative command interfaces202211,341,067Coordinating memory operations using memory-device-generated reference signals202211,328,764Memory system topologies including a memory die stack202211,302,371Memory systems and methods for dividing physical memory locations into temporal memory locations202211,289,139Memory components and controllers that calibrate multiphase synchronous timing references202211,211,105Memory device comprising programmable command-and-address and/or data interfaces202111,206,020On-die termination202111,150,982Memory error detection2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to RAMBUS INC (37)· patent assignee history
2021–2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RAMBUS INC | 37 | 2021–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 37 | 2021–2025 |