Inventor
Vivek Tiwari
Inventor
San Jose, CA, US
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing41%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use30%
G11CStatic stores15%
G06KGraphical data reading4%
G06TImage data processing or generation, in general4%
G06VImage or video recognition or understanding4%
G09GArrangements or circuits for control of indicating devices using static means to present variable information4%
PatentTitleYear
11,074,980Non-volatile memory device with stored index information202110,591,971Adaptive multi-resolution for graphics202010,152,632Dynamic brightness and resolution control in virtual environments20187,742,910'Mechanism for estimating and controlling di/dt-induced power supply voltage variations'20107,685,451'Method and apparatus to limit current-change induced voltage changes in a microcircuit'20107,281,140'Digital throttle for multiple operating points'20077,236,920'Mechanism for estimating and controlling di/dt-induced power supply voltage variations'20077,035,785'Mechanism for estimating and controlling di/dt-induced power supply voltage variations'20067,020,590'Simulation of di/dt-induced power supply voltage variation'20066,931,559'Multiple mode power throttle mechanism'20056,636,976'Mechanism to control di/dt for a microprocessor'20036,609,209'Method and apparatus for reducing the power consumed by a processor by gating the clock signal to pipeline stages'20036,577,524'Memory structures having selectively disabled portions for power conservation'20036,473,326'Memory structures having selectively disabled portions for power conservation'20026,298,002'Memory structures having selectively disabled portions for power conservation'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2020Patents assigned to INTEL CORP (14)· patent assignee history
2001–2003Based in Santa Clara, CA, US· patent location history
2003Based in Foster City, CA, US· patent location history
2005–2010Based in San Jose, CA, US· patent location history
2018–2020Based in Sunnyvale, CA, US· patent location history
2021Patents assigned to SILICON STORAGE TECH INC (1)· patent assignee history
2021Based in Dublin, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 14 | 2001–2020 |
| SILICON STORAGE TECH INC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 7 | 2005–2010 |
| Santa Clara, California, US | 4 | 2001–2003 |
| Sunnyvale, California, US | 2 | 2018–2020 |
| Dublin, California, US | 1 | 2021 |
| Foster City, California, US | 1 | 2003 |