Inventor

William V. Huott

Inventor

Holmes, NY, US

Overview

82→

Patents

1995–2021

Patent span

Physics

Primary field (CPC G)

Patents· 82 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores32%

G01RMeasuring electric variables29%

G06FElectric digital data processing22%

H03KPulse technique8%

H03MCoding3%

H04BTransmission2%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

Y02PClimate change mitigation technologies in the production or processing of goods2%

H03HImpedance networks, e.g. resonant circuits1%

H10NElectric solid-state devices not otherwise provided for1%

PatentTitleYear

10,998,075Built-in self-test for bit-write enabled memory arrays2021 10,971,242Sequential error capture during memory test2021 10,949,295Implementing dynamic SEU detection and correction method and circuit2021 10,896,081Implementing SEU detection method and circuit2021 10,897,239Granular variable impedance tuning2021 10,890,623Power saving scannable latch output driver2021 10,585,672Memory device command-address-control calibration2020 10,371,747Physically aware scan diagnostic logic and power saving circuit insertion2019 10,373,678SRAM margin recovery during burn-in2019 10,332,591SRAM margin recovery during burn-in2019 10,324,879Mitigation of side effects of simultaneous switching of input/output (I/O data signals2019 10,229,738SRAM bitline equalization using phase change material2019 10,163,493SRAM margin recovery during burn-in2018 10,157,672SRAM bitline equalization using phase change material2018 10,061,886Physically aware test patterns in semiconductor fabrication2018 9,983,261Partition-able storage of test results using inactive storage elements2018 9,922,163'Physically aware test patterns in semiconductor fabrication'2018 9,857,416'Voltage rail monitoring to detect electromigration'2018 9,762,213'Initializing scannable and non-scannable latches from a common clock buffer'2017 9,762,212'Initializing scannable and non-scannable latches from a common clock buffer'2017 9,753,076'Voltage rail monitoring to detect electromigration'2017 9,746,516'Collecting diagnostic data from chips'2017 9,697,910'Multi-match error detection in content addressable memory testing'2017 9,627,012'Shift register with opposite shift data and shift clock directions'2017 9,557,381'Physically aware insertion of diagnostic circuit elements'2017 9,548,773'Mitigation of EMI/ESD-caused transmission errors on an electronic circuit'2017 9,372,232'Collecting diagnostic data from chips'2016 9,355,746'Built-in testing of unused element on chip'2016 9,285,423'Managing chip testing data'2016 9,201,727'Error protection for a data bus'2015 9,136,019'Built-in testing of unused element on chip'2015 9,043,683'Error protection for integrated circuits'2015 9,041,428'Placement of storage cells on an integrated circuit'2015 9,021,328'Shared error protection for register banks'2015 8,942,052'Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages'2015 8,327,207'Memory testing system'2012 8,117,579'LSSD compatibility for GSD unified global clock buffers'2012 8,055,960'Self test apparatus for identifying partially defective memory'2011 8,001,411'Generating a local clock domain using dynamic controls'2011 7,793,173'Efficient memory product for test and soft repair of SRAM with redundancy'2010 7,752,514'Methods and apparatus for testing a scan chain to isolate defects'2010 7,650,535'Array delete mechanisms for shipping a microprocessor with defective arrays'2010 7,606,060'Eight transistor SRAM cell with improved stability requiring only one word line'2009 7,536,613'BIST address generation architecture for multi-port memories'2009 7,529,997'Method for self-correcting cache using line delete, data logging, and fuse repair correction'2009 7,478,297'Merged MISR and output register without performance impact for circuits under test'2009 7,437,626'Efficient method of test and soft repair of SRAM with redundancy'2008 7,434,130'Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection'2008 7,400,555'Built in self test circuit for measuring total timing uncertainty in a digital data path'2008 7,368,958'Methods and systems for locally generating non-integral divided clocks with centralized state machines'2008 7,366,953'Self test method and apparatus for identifying partially defective memory'2008 7,355,460'Method for locally generating non-integral divided clocks with centralized state machines'2008 7,319,348'Circuits for locally generating non-integral divided clocks with centralized state machines'2008 7,313,744'Methods and apparatus for testing a scan chain to isolate defects'2007 7,305,602'Merged MISR and output register without performance impact for circuits under test'2007 7,295,458'Eight transistor SRAM cell with improved stability requiring only one word line'2007 7,275,194'Clock duty cycle based access timer combined with standard stage clocked output register'2007 7,260,757'System and method for testing electronic devices on a microchip'2007 7,257,745'Array self repair using built-in self test techniques'2007 7,219,275'Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy'2007 7,178,075'High-speed level sensitive scan design test scheme with pipelined test clocks'2007 7,139,944'Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability'2006 7,129,764'System and method for local generation of a ratio clock'2006 7,099,201'Multifunctional latch circuit for use with both SRAM array and self test device'2006 6,978,408'Generating array bit-fail maps without a tester using on-chip trace arrays'2005 6,912,665'Automatic timing analyzer'2005 6,865,501'Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection'2005 6,836,865'Method and apparatus for facilitating random pattern testing of logic structures'2004 6,728,914'Random path delay testing methodology'2004 6,671,644'Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection'2003 6,662,324'Global transition scan based AC method'2003 6,629,281'Method and system for at speed diagnostics and bit fail mapping'2003 6,629,280'Method and apparatus for delaying ABIST start'2003 6,625,769'Method for IC fault analysis using programmable built-in self test and optical emission'2003 6,314,540'Partitioned pseudo-random logic test for improved manufacturability of semiconductor chips'2001 6,311,311'Multiple input shift register (MISR) signatures used on architected registers to detect interim functional errors on instruction stream test'2001 6,125,465'Isolation/removal of faults during LBIST testing'2000 5,805,789'Programmable computer system element with built-in self test method and apparatus for repair during power-on'1998 5,661,732'Programmable ABIST microprocessor for testing arrays with two logical views'1997 5,659,551'Programmable computer system element with built-in self test method and apparatus for repair during power-on'1997 5,633,877'Programmable built-in self test method and controller for arrays'1997 5,420,467'Programmable delay clock chopper/stretcher with fast recovery'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2021Patents assigned to IBM (81)· patent assignee history

1995Based in Wappingers Falls, NY, US· patent location history

1997–2021Based in Holmes, NY, US· patent location history

2004Patents assigned to CADENCE DESIGN SYSTEMS INC (1)· patent assignee history

2012Patents assigned to BUSHARD LOUIS BERNARD (1)· patent assignee history

2012Patents assigned to DHONG SANG HOO (1)· patent assignee history

2012Patents assigned to DIETER WENDEL (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	81	1995–2021
BUSHARD LOUIS BERNARD	1	2012
CADENCE DESIGN SYSTEMS INC	1	2004
DHONG SANG HOO	1	2012
DIETER WENDEL	1	2012

Locations

Location	Patents	Span
Holmes, New York, US	81	1997–2021
Wappingers Falls, New York, US	1	1995