Inventor
Lyndon R. Logan
Inventor
Poughkeepsie, NY, US
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H01LSemiconductor devices16%
G01RMeasuring electric variables13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
G01BMeasuring length, thickness or similar linear dimensions3%
H10BElectronic memory devices3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution3%
PatentTitleYear
9,972,550Source/drain epitaxial electrical monitor20189,941,179Capacitive measurements of divots in semiconductor devices20189,852,956Extraction of resistance associated with laterally diffused dopant profiles in CMOS devices20179,318,622'Fin-type PIN diode array'20169,105,707'ZRAM heterochannel memory'20159,059,190'Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations'20158,709,833'Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations'20148,000,935'Diagnostic method for root-cause analysis of FET performance variation'20117,587,298'Diagnostic method for root-cause analysis of FET performance variation'20096,946,710'Method and structure to reduce CMOS inter-well leakage'20056,756,637'Method of controlling floating body effects in an asymmetrical SOI device'20046,686,252'Method and structure to reduce CMOS inter-well leakage'20046,372,559'Method for self-aligned vertical double-gate MOSFET'20026,144,081'Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures'20005,567,553'Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2018Patents assigned to IBM (13)· patent assignee history
1996–2000Based in Wappingers Falls, NY, US· patent location history
2002–2005Based in Essex Junction, VT, US· patent location history
2009–2018Based in Poughkeepsie, NY, US· patent location history
2011Based in Hopewell Junction, NY, US· patent location history
2014Patents assigned to LOGAN LYNDON R (1)· patent assignee history
2014Patents assigned to NOWAK EDWARD J (1)· patent assignee history
2014Patents assigned to ROBISON ROBERT R (1)· patent assignee history
2017–2018Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 13 | 1996–2018 |
| GLOBALFOUNDRIES INC | 3 | 2017–2018 |
| LOGAN LYNDON Rself | 1 | 2014 |
| NOWAK EDWARD J | 1 | 2014 |
| ROBISON ROBERT R | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 8 | 2009–2018 |
| Essex Junction, VT, US | 4 | 2002–2005 |
| Wappingers Falls, New York, US | 2 | 1996–2000 |
| Hopewell Junction, New York, US | 1 | 2011 |