Inventor

Qian Fu

Inventor

Pleasanton, CA, US

Overview

47→

Patents

2009–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 47 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1031%

H01LSemiconductor devices25%

H01JElectric discharge tubes or discharge lamps16%

H10BElectronic memory devices7%

C23CCoating metallic material5%

H05HPlasma technique4%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

H10DInorganic electric semiconductor devices1%

H10NElectric solid-state devices not otherwise provided for1%

PatentTitleYear

10,938,257Stator for motor, motor and compressor2021 10,763,142System and method for determining field non-uniformities of a wafer processing chamber using a wafer processing parameter2020 10,658,194Silicon-based deposition for semiconductor processing2020 10,446,394Spacer profile control using atomic layer deposition in a multiple patterning process2019 10,354,888Method and apparatus for anisotropic tungsten etching2019 10,242,845Near-substrate supplemental plasma density generation with low bias voltage within inductively coupled plasma processing chamber2019 10,177,003Methods and systems for plasma etching using bi-modal process gas composition responsive to plasma power level2019 10,020,183Edge roughness reduction2018 9,997,366Silicon oxide silicon nitride stack ion-assisted etch2018 9,991,128Atomic layer etching in continuous plasma2018 9,941,123Post etch treatment to prevent pattern collapse2018 9,859,127'Line edge roughness improvement with photon-assisted plasma process'2018 9,852,924Line edge roughness improvement with sidewall sputtering2017 9,824,896'Methods and systems for advanced ion control for etching processes'2017 9,767,991'Methods and systems for independent control of radical density, ion density, and ion energy in pulsed plasma semiconductor device fabrication'2017 9,761,459'Systems and methods for reverse pulsing'2017 9,741,563'Hybrid stair-step etch'2017 RE046464'Method for forming stair-step structures'2017 9,691,625'Methods and systems for plasma etching using bi-modal process gas composition responsive to plasma power level'2017 9,673,057'Method for forming stair-step structures'2017 9,646,844'Method for forming stair-step structures'2017 9,633,867'Method and apparatus for anisotropic tungsten etching'2017 9,607,848'Etch process with pre-etch transient conditioning'2017 9,583,357'Systems and methods for reverse pulsing'2017 9,530,658'Continuous plasma etch process'2016 9,466,502'Line width roughness improvement with noble gas plasma'2016 9,418,869'Method to etch a tungsten containing layer'2016 9,275,872'Method for forming stair-step structures'2016 9,263,284'Line width roughness improvement with noble gas plasma'2016 9,257,296'Etch process with pre-etch transient conditioning'2016 9,142,417'Etch process with pre-etch transient conditioning'2015 9,129,902'Continuous plasma ETCH process'2015 9,059,116'Etch with pulsed bias'2015 8,901,004'Plasma etch method to reduce micro-loading'2014 8,802,571'Method of hard mask CD control by Ar sputtering'2014 8,753,804'Line width roughness improvement with noble gas plasma'2014 8,609,546'Pulsed bias plasma process to control microloading'2013 8,535,549'Method for forming stair-step structures'2013 8,518,282'Method of controlling etch microloading for a tungsten-containing layer'2013 8,440,573'Method and apparatus for pattern collapse free wet processing of semiconductor devices'2013 8,431,461'Silicon nitride dry trim without top pulldown'2013 8,329,051'Method for forming stair-step structures'2012 8,216,388'Extending storage time of removed plasma chamber components prior to cleaning thereof'2012 8,124,538'Selective etch of high-k dielectric material'2012 7,976,641'Extending storage time of removed plasma chamber components prior to cleaning thereof'2011 7,682,979'Phase change alloy etch'2010 7,629,255'Method for reducing microloading in etching high aspect ratio structures'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2020Patents assigned to LAM RES CORP (46)· patent assignee history

2009–2014Based in Fremont, CA, US· patent location history

2012–2015Patents assigned to FU QIAN (12)· patent assignee history

2012–2014Patents assigned to LIU SHENJIAN (6)· patent assignee history

2012–2015Patents assigned to LEE WONCHUL (5)· patent assignee history

2012–2020Based in Pleasanton, CA, US· patent location history

2013Patents assigned to PU BRYAN (2)· patent assignee history

2021Based in Guangdong, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
LAM RES CORP	46	2009–2020
FU QIANself	12	2012–2015
LIU SHENJIAN	6	2012–2014
LEE WONCHUL	5	2012–2015
PU BRYAN	2	2013

Locations

Location	Patents	Span
Pleasanton, California, US	39	2012–2020
Fremont, California, US	7	2009–2014
Guangdong, CN	1	2021