LexDanaLexDanabeta
Inventor

Darryl G. Walker

Inventor
San Jose, CA, US

Overview

80→
Patents
1993–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 80 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores23%
H10BElectronic memory devices11%
G01KMeasuring temperature10%
H01LSemiconductor devices10%
H10DInorganic electric semiconductor devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H03KPulse technique7%
G01RMeasuring electric variables5%
Y10TTechnical subjects covered by former us classification4%
H05BElectric heating2%
PatentTitleYear
10,665,294Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits202010,656,028Semiconductor device having variable parameter selection based on temperature and test method202010,622,085Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor202010,605,672Semiconductor device having temperature circuit that sets temperature ranges and is disabled upon power supply transition202010,497,430Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on power supply voltage detection circuits201910,453,823Package including a plurality of stacked semiconductor devices, an interposer and interface connections201910,418,346Package including a plurality of stacked semiconductor devices having area efficient ESD protection201910,403,384Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor201910,365,318Testing and setting performance parameters in a semiconductor device and method therefor201910,262,976Package including a plurality of stacked semiconductor devices, an interposer and interface connections201910,260,962Semiconductor device having temperature sensor circuit that detects a temperature range upper limit value and a temperature range lower limit value201910,262,975Package including a plurality of stacked semiconductor devices, an interposer and interface connections201910,177,121Package including a plurality of stacked semiconductor devices, an interposer and interface connections201910,163,524Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor201810,141,058Multi-chip non-volatile semiconductor memory package including heater and sensor elements201810,134,720Package including a plurality of stacked semiconductor devices having area efficient ESD protection201810,128,215Package including a plurality of stacked semiconductor devices having area efficient ESD protection201810,115,455Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits201810,115,710Package including a plurality of stacked semiconductor devices, an interposer and interface connections201810,049,727Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits201810,014,049Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits201810,006,959Testing and setting performance parameters in a semiconductor device and method therefor20189,997,513Package including a plurality of stacked semiconductor devices having area efficient ESD protection20189,958,341Semiconductor device having temperature sensor circuit that detects a temperature range upper limit value and a temperature range lower limit value20189,940,999Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits20189,939,330Semiconductor device having subthreshold operating circuits including a back body bias potential based on temperature range20189,933,317Power up of semiconductor device having a temperature circuit and method therefor20189,929,127'Package including a plurality of stacked semiconductor devices an interposer and interface connections'20189,928,925'Multi-chip non-volatile semiconductor memory package including heater and sensor elements'20189,842,830'Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture'20179,810,585'Semiconductor device having a temperature circuit that provides a plurality of temperature operating ranges'20179,772,232'Semiconductor device having temperature sensor circuit that detects a temperature range upper limit value and a temperature range lower limit value'20179,766,135'Semiconductor device having variable parameter selection based on temperature and test method'20179,711,500'Package including a plurality of stacked semiconductor devices having area efficient ESD protection'20179,685,427'Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture'20179,658,277'Testing and setting performance parameters in a semiconductor device and method therefor'20179,645,191'Testing and setting performance parameters in a semiconductor device and method therefor'20179,631,982'Semiconductor device having temperature sensor circuits'20179,613,719'Multi-chip non-volatile semiconductor memory package including heater and sensor elements'20179,607,969'Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture'20179,548,126'Multi-chip non-volatile semiconductor memory package including heater and sensor elements'20179,508,692'Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture'20169,455,189'Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture'20169,431,088'Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture'20169,378,778'Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture'20169,286,991'Multi-chip non-volatile semiconductor memory package including heater and sensor elements'20169,274,007'Semiconductor device having temperature sensor circuits'20169,194,754'Power up of semiconductor device having a temperature circuit and method therefor'20158,497,453'Semiconductor device having variable parameter selection based on temperature'20138,308,359'Semiconductor device having variable parameter selection based on temperature and test method'20128,081,532'Semiconductor device having variable parameter selection based on temperature and test method'20118,049,145'Semiconductor device having variable parameter selection based on temperature and test method'20118,040,742'Semiconductor device having variable parameter selection based on temperature and test method'20118,005,641'Temperature sensing circuit with hysteresis and time delay'20117,953,573'Semiconductor device having variable parameter selection based on temperature and test method'20117,760,570'Semiconductor device having variable parameter selection based on temperature and test method'20107,720,627'Semiconductor device having variable parameter selection based on temperature and test method'20107,654,736'Semiconductor device having variable parameter selection based on temperature and test method'20107,639,548'Semiconductor device having variable parameter selection based on temperature and test method'20097,603,249'Semiconductor device having variable parameter selection based on temperature and test method'20097,535,786'Semiconductor device having variable parameter selection based on temperature and test method'20097,480,588'Semiconductor device having variable parameter selection based on temperature and test method'20097,383,149'Semiconductor device having variable parameter selection based on temperature and test method'20086,967,887'Semiconductor memory device including a double-gate dynamic random access memory cell having reduced current leakage'20056,934,180'Random access memory cell having reduced current leakage and having a pass transistor control gate formed in a trench'20056,661,699'Random access memory cell having double-gate access transistor for reduced leakage current'20036,661,702'Double gate DRAM memory cell having reduced leakage current'20036,384,439'DRAM memory cell and array having pass transistors with recessed channels'20026,207,985'DRAM memory cell and array having pass transistors with surrounding gate'20016,127,849'Simultaneous bi-directional input/output (I/O) circuit'20006,064,589'Double gate DRAM memory cell'20006,046,943'Synchronous semiconductor device output circuit with reduced data switching'20005,872,742'Staggered pipeline access scheme for synchronous random access memory'19995,808,959'Staggered pipeline access scheme for synchronous random access memory'19985,576,633'Block specific spare circuit'19965,548,225'Block specific spare circuit'19965,508,962'Apparatus and method for an active field plate bias generator'19965,342,799'Substrate slew circuit process'19945,313,111'Substrate slew circuit providing reduced electron injection'19945,266,843'Substrate slew circuit'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2002Patents assigned to TEXAS INSTRUMENTS INC (9)· patent assignee history
1993–1994Based in Dallas, TX, US· patent location history
1996Based in Sugar Land, TX, US· patent location history
1998–1999Based in Santa Clara, CA, US· patent location history
2000–2020Based in San Jose, CA, US· patent location history
2000Based in Sunnyvale, CA, US· patent location history
2005–2020Patents assigned to WALKER DARRYL G (48)· patent assignee history
2008–2010Patents assigned to WALKER DARRYL (7)· patent assignee history
2011Patents assigned to AGERSONN RALL GROUP LLC (4)· patent assignee history
2019–2020Patents assigned to SAMSUNG ELECTRONICS CO LTD (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
WALKER DARRYL Gself482005–2020
TEXAS INSTRUMENTS INC91993–2002
WALKER DARRYLself72008–2010
SAMSUNG ELECTRONICS CO LTD62019–2020
AGERSONN RALL GROUP LLC42011
Locations
LocationPatentsSpan
San Jose, California, US702000–2020
Sugar Land, Texas, US31996
Dallas, Texas, US31993–1994
Sunnyvale, California, US22000
Santa Clara, California, US21998–1999