Inventor
David A. Fotland
Inventor
San Jose, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing46%
G06TImage data processing or generation, in general11%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
G06KGraphical data reading9%
G06VImage or video recognition or understanding9%
H04NPictorial communication, e.g. television6%
G01SRadio direction-finding3%
G11CStatic stores3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
PatentTitleYear
10,200,572Motion detection201910,007,860Identifying items in images using regions-of-interest20189,953,242Identifying items in images using regions-of-interest20189,832,452Robust user detection and tracking20179,690,384'Fingertip location determinations for gesture input'20179,632,655'No-touch cursor for item selection'20179,269,012'Multi-tracker object tracking'20169,081,571'Gesture detection management for an electronic device'20157,925,869'Instruction-level multithreading according to a predetermined fixed schedule in an embedded processor using zero-time context switching'20117,822,950'Thread cancellation and recirculation in a computer processor for avoiding pipeline stalls'20107,546,442'Fixed length memory to memory arithmetic and architecture for direct memory access using fixed length instructions'20097,308,686'Software input/output using hard real time threads'20077,120,783'System and method for reading and writing a thread state in a multithreaded central processing unit'20067,082,519'System and method for instruction level multithreading scheduling in a embedded processor'20067,047,396'Fixed length memory to memory arithmetic and architecture for a communications embedded processor system'20066,408,380'Execution of an instruction to load two independently selected registers in a single cycle'20025,987,576'Method and apparatus for generating and distributing clock signals with minimal skew'19994,873,627'Method and means for conditional storing of data in a reduced instruction set computer'19894,747,046'Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–1999Patents assigned to HEWLETT PACKARD CO (3)· patent assignee history
1988–2019Based in San Jose, CA, US· patent location history
2002Patents assigned to INST THE DEV OF EMERGING ARCHI (1)· patent assignee history
2006–2011Patents assigned to UBICOM INC (7)· patent assignee history
2015–2019Patents assigned to AMAZON TECH INC (8)· patent assignee history
2017Patents assigned to FOTLAND DAVID ALLEN (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| AMAZON TECH INC | 8 | 2015–2019 |
| UBICOM INC | 7 | 2006–2011 |
| HEWLETT PACKARD CO | 3 | 1988–1999 |
| FOTLAND DAVID ALLENself | 1 | 2017 |
| INST THE DEV OF EMERGING ARCHI | 1 | 2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 19 | 1988–2019 |