Inventor
Gerhard Kunkel
Inventor
Radebeul, DE
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G03Fprimary
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices33%
H10BElectronic memory devices21%
H10DInorganic electric semiconductor devices14%
G11CStatic stores7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G01MTesting static or dynamic balance of machines or structures2%
G01NInvestigating or analysing materials by determining their chemical or physical properties2%
G02BOptical elements, systems or apparatus2%
G03CPhotosensitive materials for photographic purposes2%
PatentTitleYear
8,362,537'Memory devices including semiconductor pillars'20137,482,110'Method for adapting structure dimensions during the photolithographic projection of a pattern of structure elements onto a semiconductor wafer'20097,465,522'Photolithographic mask having half tone main features and perpendicular half tone assist features'20087,462,426'Method for producing a phase mask'20087,248,351'Optimizing light path uniformity in inspection systems'20077,074,529'Phase-shift mask'20066,911,687'Buried bit line-field isolation defined active semiconductor areas'20056,842,222'Method of reducing pitch on semiconductor wafer'20056,809,800'Apparatus for patterning a semiconductor wafer'20046,727,989'Enhanced overlay measurement marks for overlay alignment and exposure tool condition control'20046,606,151'Grating patterns and method for determination of azimuthal and radial aberration'20036,590,657'Semiconductor structures and manufacturing methods'20036,566,219'Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening'20036,558,883'Apparatus and method for patterning a semiconductor wafer'20036,511,791'Multiple exposure process for formation of dense rectangular arrays'20036,451,508'Plural interleaved exposure process for increased feature aspect ratio in dense arrays'20026,420,272'Method for removal of hard mask used to define noble metal electrode'20026,383,691'Photomask and method for increasing image aspect ratio while relaxing mask fabrication requirements'20026,379,869'Method of improving the etch resistance of chemically amplified photoresists by introducing silicon after patterning'20026,365,328'Semiconductor structure and manufacturing method'20026,282,116'Dynamic random access memory'20016,211,544'Memory cell layout for reduced interaction between storage nodes and transistors'20016,136,660'Stacked capacitator memory cell and method of fabrication'20006,118,683'Dynamic random access memory cell layout'20006,083,788'Stacked capacitor memory cell and method of manufacture'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2005Patents assigned to IBM (9)· patent assignee history
2000–2003Patents assigned to INFINEON TECHNOLOGIES CORP (8)· patent assignee history
2000–2004Based in Fishkill, NY, US· patent location history
2001–2013Based in Radebeul, DE· patent location history
2002–2009Patents assigned to INFINEON TECHNOLOGIES AG (14)· patent assignee history
2007Based in Dresden, DE· patent location history
2013Patents assigned to BAARS PETER (1)· patent assignee history
2013Patents assigned to KUNKEL GERHARD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 14 | 2002–2009 |
| IBM | 9 | 2000–2005 |
| INFINEON TECHNOLOGIES CORP | 8 | 2000–2003 |
| BAARS PETER | 1 | 2013 |
| KUNKEL GERHARDself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Radebeul, DE | 15 | 2001–2013 |
| Fishkill, New York, US | 9 | 2000–2004 |
| Dresden, DE | 1 | 2007 |