Inventor

William T. Chou

Inventor

Cupertino, CA, US

Overview

38→

Patents

1994–2005

Patent span

Electricity

Primary field (CPC H)

Patents· 38 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H05Kprimary

H05KPrinted circuits33%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%

Y10TTechnical subjects covered by former us classification10%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices6%

G02BOptical elements, systems or apparatus4%

C25DProcesses for the electrolytic or electrophoretic production of coatings2%

H01GCapacitors2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%

PatentTitleYear

6,845,184'Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making'2005 6,733,685'Methods of planarizing structures on wafers and substrates by polishing'2004 6,690,845'Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making'2004 6,662,443'Method of fabricating a substrate with a via connection'2003 6,611,635'Opto-electronic substrates with electrical and optical interconnections and methods for making'2003 6,343,171'Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making'2002 6,239,485'Reduced cross-talk noise high density signal interposer with power and ground wrap'2001 6,226,171'Power conducting substrates with high-yield integrated substrate capacitor'2001 6,221,567'Method of patterning polyamic acid layers'2001 6,197,664'Method for electroplating vias or through holes in substrates having conductors on both sides'2001 6,187,652'Method of fabrication of multiple-layer high density substrate'2001 6,102,710'Controlled impedance interposer substrate and method of making'2000 6,081,026'High density signal interposer with power and ground wrap'2000 6,039,889'Process flows for formation of fine structure layer pairs on flexible films'2000 5,942,373'Pattern or via structure formed through supplemental electron beam exposure and development to remove image residue'1999 5,930,890'Structure and fabrication procedure for a stable post'1999 5,916,453'Methods of planarizing structures on wafers and substrates by polishing'1999 5,891,354'Methods of etching through wafers and substrates with a composite etch stop layer'1999 5,854,534'Controlled impedence interposer substrate'1998 5,789,140'Method of forming a pattern or via structure utilizing supplemental electron beam exposure and development to remove image residue'1998 5,778,529'Method of making a multichip module substrate'1998 5,773,889'Wire interconnect structures for connecting an integrated circuit to a substrate'1998 5,746,903'Wet chemical processing techniques for plating high aspect ratio features'1998 5,722,162'Fabrication procedure for a stable post'1998 5,660,957'Electron-beam treatment procedure for patterned mask layers'1997 5,656,414'Methods of forming tall, high-aspect ratio vias and trenches in photo-imageable materials, photoresist materials, and the like'1997 5,652,693'Substrate with thin film capacitor and insulating plug'1997 5,544,017'Multichip module substrate'1996 5,536,362'Wire interconnect structures for connecting an integrated circuit to a substrate'1996 5,475,262'Functional substrates for packaging semiconductor chips'1995 5,458,731'Method for fast and non-destructive examination of etched features'1995 5,455,064'Process for fabricating a substrate with thin film capacitor and insulating plug'1995 5,419,038'Method for fabricating thin-film interconnector'1995 5,406,446'Thin film capacitor'1995 5,382,827'Functional substrates for packaging semiconductor chips'1995 5,376,586'Method of curing thin films of organic dielectric material'1994 5,334,804'Wire interconnect structures for connecting an integrated circuit to a substrate'1994 5,323,520'Process for fabricating a substrate with thin film capacitor'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2005Patents assigned to FUJITSU LTD (38)· patent assignee history

1994–2005Based in Cupertino, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
FUJITSU LTD	38	1994–2005

Locations

Location	Patents	Span
Cupertino, California, US	38	1994–2005