LexDanaLexDanabeta
Inventor

Jaime A. Bayan

Inventor
Palo Alto, CA, US

Overview

63→
Patents
1992–2014
Patent span
Electricity
Primary field (CPC H)

Patents· 63 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1065%
Y10TTechnical subjects covered by former us classification13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
C25DProcesses for the electrolytic or electrophoretic production of coatings2%
H05KPrinted circuits2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B65GTransport or storage devices, e.g. conveyors for loading or tipping, shop conveyor systems or pneumatic tube conveyors1%
H01LSemiconductor devices1%
H10DInorganic electric semiconductor devices1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
PatentTitleYear
8,857,047'Thin foil semiconductor package'20148,747,640'Foil plating for semiconductor packaging'20148,679,896'DC/DC converter power module package incorporating a stacked controller and construction methodology'20148,450,149'Stacked leadframe implementation for DC/DC convertor power module incorporating a stacked controller and stacked leadframe construction methodology'20138,375,577'Method of making foil based semiconductor package'20138,377,267'Foil plating for semiconductor packaging'20138,341,828'Thin foil semiconductor package'20138,298,871'Method and leadframe for packaging integrated circuits'20128,293,573'Microarray package with plated contact pedestals'20128,222,716'Multiple leadframe package'20128,101,470'Foil based semiconductor package'20127,944,032'Integrated circuit package with molded insulation'20117,923,825'Integrated circuit package'20117,893,523'Microarray package with plated contact pedestals'20117,859,090'Die attach method and leadframe structure'20107,836,586'Thin foil semiconductor package'20107,705,476'Integrated circuit package'20107,678,617'Universal laminator'20107,671,452'Microarray package with plated contact pedestals'20107,619,303'Integrated circuit package'20097,612,435'Method of packaging integrated circuits'20097,608,482'Integrated circuit package with molded insulation'20097,598,122'Die attach method and microarray leadframe structure'20097,491,625'Gang flipping for IC packaging'20097,432,583'Leadless leadframe package substitute and stack package'20087,227,245'Die attach pad for use in semiconductor manufacturing and method of making same'20077,186,588'Method of fabricating a micro-array integrated circuit package'20077,181,835'Universal clamping mechanism'20077,102,209'Substrate for use in semiconductor manufacturing and method of making same'20067,087,986'Solder pad configuration for use in a micro-array integrated circuit package'20067,064,419'Die attach region for use in a micro-array integrated circuit package'20067,045,035'Post singulation die separation apparatus and method for bulk feeding operation'20067,023,074'Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP)'20066,963,124'Locking of mold compound to conductive substrate panels'20056,932,136'Post singulation die separation apparatus and method for bulk feeding operation'20056,933,174'Leadless leadframe package design that provides a greater structural integrity'20056,930,377'Using adhesive materials as insulation coatings for leadless lead frame semiconductor packages'20056,916,688'Apparatus and method for a wafer level chip scale package heat sink'20056,872,599'Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP)'20056,818,970'Leadless leadframe package design that provides a greater structural integrity'20046,808,961'Locking of mold compound to conductive substrate panels'20046,797,540'Dap isolation process'20046,781,243'Leadless leadframe package substitute and stack package'20046,777,788'Method and structure for applying thick solder layer onto die attach pad'20046,698,088'Universal clamping mechanism'20046,686,652'Locking lead tips and die attach pad for a leadless package apparatus and method'20046,677,667'Leadless leadframe package design that provides a greater structural integrity'20046,674,156'Multiple row fine pitch leadless leadframe package with use of half-etch process'20046,664,615'Method and apparatus for lead-frame based grid array IC packaging'20036,617,197'Multi row leadless leadframe package'20036,576,989'Locking of mold compound to conductive substrate panels'20036,551,048'Off-load system for semiconductor devices'20036,483,180'Lead frame design for burr-free singulation of molded array packages'20026,452,255'Low inductance leadless package'20026,448,107'Pin indicator for leadless leadframe packages'20026,399,415'Electrical isolation in panels of leadless IC packages'20026,372,539'Leadless packaging process using a conductive substrate'20026,364,089'Multi-station rotary die handling device'20026,348,726'Multi row leadless leadframe package'20026,001,723'Application of wire bond loop as integrated circuit package component interconnect'19995,780,772'Solution to mold wire sweep in fine pitch devices'19985,569,956'Interposer connecting leadframe and integrated circuit'19965,146,310'Thermally enhanced leadframe'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2014Patents assigned to NAT SEMICONDUCTOR CORP (59)· patent assignee history
1992–2014Based in Palo Alto, CA, US· patent location history
2010–2014Based in San Francisco, CA, US· patent location history
2012–2013Patents assigned to BAYAN JAIME A (6)· patent assignee history
2012–2013Patents assigned to TU NGHIA THUC (5)· patent assignee history
2012–2014Patents assigned to TEXAS INSTRUMENTS INC (4)· patent assignee history
2012–2013Patents assigned to CHIN DAVID (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
NAT SEMICONDUCTOR CORP591992–2014
BAYAN JAIME Aself62012–2013
TU NGHIA THUC52012–2013
TEXAS INSTRUMENTS INC42012–2014
CHIN DAVID32012–2013
Locations
LocationPatentsSpan
Palo Alto, California, US511992–2014
San Francisco, California, US122010–2014