Inventor

Christopher B. Wilkerson

Inventor

Portland, OR, US

Overview

58→

Patents

2001–2021

Patent span

Physics

Primary field (CPC G)

Patents· 58 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing63%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use17%

G11CStatic stores7%

G01RMeasuring electric variables4%

H03KPulse technique4%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%

PatentTitleYear

11,042,403Platform auto-configuration and tuning2021 10,860,244Method and apparatus for multi-level memory early page demotion2020 10,678,692Method and system for coordinating baseline and secondary prefetchers2020 10,606,755Method and system for performing data movement operations with read snapshot and in place write update2020 10,528,473Disabling cache portions during low voltage operations2020 10,521,236Branch prediction based on coherence operations in processors2019 10,496,544Aggregated write back in a direct mapped two level memory2019 10,482,017Processor, method, and system for cache partitioning and control for accurate performance monitoring and optimization2019 10,452,551Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register2019 10,261,901Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory2019 10,229,060Instruction and logic for software hints to improve hardware prefetcher effectiveness2019 10,210,202Recognition of free-form gestures from orientation tracking of a handheld or wearable device2019 10,120,806Multi-level system memory with near memory scrubbing based on predicted far memory idle time2018 10,108,549Method and apparatus for pre-fetching data in a system having a multi-level system memory2018 10,102,134Instruction and logic for run-time evaluation of multiple prefetchers2018 10,024,916Sequential circuit with error detection2018 10,019,360Hardware predictor using a cache line demotion instruction to reduce performance inversion in core-to-core data transfers2018 10,007,620System and method for cache replacement using conservative set dueling2018 9,921,961'Multi-level memory management'2018 9,921,972'Method and apparatus for implementing a heterogeneous memory subsystem'2018 9,811,555'Recognition of free-form gestures from orientation tracking of a handheld or wearable device'2017 9,710,391'Methods and apparatuses for efficient load processing using buffers'2017 9,703,708'System and method for thread scheduling on reconfigurable processor cores'2017 9,678,878'Disabling cache portions during low voltage operations'2017 9,594,625'Sequential circuit with error detection'2017 9,583,182'Multi-level memory management'2017 9,472,248'Method and apparatus for implementing a heterogeneous memory subsystem'2016 9,417,879'Systems and methods for managing reconfigurable processor cores'2016 9,378,021'Instruction and logic for run-time evaluation of multiple prefetchers'2016 9,286,224'Constraining prefetch requests to a processor socket'2016 9,229,872'Semiconductor chip with adaptive BIST cache testing during runtime'2016 9,223,710'Read-write partitioning of cache memory'2015 9,189,014'Sequential circuit with error detection'2015 8,966,345'Selective error correction in memory to reduce power consumption'2015 8,868,836'Reducing minimum operating voltage through hybrid cache design'2014 8,848,858'Integrated non-volatile monotonic counters'2014 8,806,285'Dynamically allocatable memory error mitigation'2014 8,719,502'Adaptive self-repairing cache'2014 8,640,005'Method and apparatus for using cache memory in a system that supports a low power state'2014 8,452,946'Methods and apparatuses for efficient load processing using buffers'2013 8,291,168'Disabling cache portions during low voltage operations'2012 8,103,830'Disabling cache portions during low voltage operations'2012 7,206,918'Address predicting apparatus and methods'2007 7,114,059'System and method to bypass execution of instructions involving unreliable data during speculative execution'2006 7,111,132'Parallel processing apparatus, system, and method utilizing correlated data value pairs'2006 6,957,304'Runahead allocation protection (RAP)'2005 6,954,848'Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately'2005 6,931,490'Set address correlation address predictors for long memory latencies'2005 6,785,797'Address predicting apparatus and methods'2004 6,782,469'Runtime critical load/data ordering'2004 6,779,108'Incorporating trigger loads in branch histories for branch prediction'2004 6,760,816'Critical loads guided data prefetching'2004 6,668,306'Non-vital loads'2003 6,662,273'Least critical used replacement with critical cache'2003 6,535,961'Spatial footprint prediction'2003 6,463,580'Parallel processing utilizing highly correlated data values'2002 6,393,525'Least recently used replacement method with protection'2002 6,205,544'Decomposition of instructions into branch and sequential code sections'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Patents assigned to INTEL CORP (58)· patent assignee history

2001–2006Based in Beaverton, OR, US· patent location history

2003–2021Based in Portland, OR, US· patent location history

2012–2017Patents assigned to WILKERSON CHRISTOPHER (5)· patent assignee history

2012–2017Patents assigned to DE VIVEK (4)· patent assignee history

2013–2016Patents assigned to WILKERSON CHRISTOPHER B (7)· patent assignee history

2014Patents assigned to ALAMELDEEN ALAA R (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	58	2001–2021
WILKERSON CHRISTOPHER Bself	7	2013–2016
WILKERSON CHRISTOPHERself	5	2012–2017
ALAMELDEEN ALAA R	4	2014
DE VIVEK	4	2012–2017

Locations

Location	Patents	Span
Portland, OR, US	53	2003–2021
Beaverton, OR, US	5	2001–2006