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Inventor

Subhas Bothra

Inventor
San Jose, CA, US

Overview

90→
Patents
1996–2012
Patent span
Electricity
Primary field (CPC H)

Patents· 90 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10DInorganic electric semiconductor devices10%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
H01FMagnets4%
B24BMachines, devices, or processes for grinding or polishing3%
H10BElectronic memory devices3%
Y10TTechnical subjects covered by former us classification2%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%
PatentTitleYear
8,274,353'Fully differential, high Q, on-chip, impedance matching section'20128,270,629'System and method allowing for safe use of a headset'20127,911,310'Fully differential, high Q, on-chip, impedance matching section'20117,614,024'Method to implement metal fill during integrated circuit design and layout'20097,489,221'Fully differential, high Q, on-chip, impedance matching section'20097,434,189'I/O driver power distribution method for reducing silicon area'20087,095,307'Fully differential, high Q, on-chip, impedance matching section'20066,916,525'Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection'20056,787,908'Pad metallization over active circuitry'20046,756,316'Semiconductor pressure transducer structures and methods for making the same'20046,717,232'Semiconductor inductor and methods for making the same'20046,710,425'Structure to increase density of MIM capacitors between adjacent metal layers in an integrated circuit'20046,649,253'Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection'20036,573,148'Methods for making semiconductor inductor'20036,569,757'Methods for forming co-axial interconnect lines in a CMOS process for high speed applications'20036,545,338'Methods for implementing co-axial interconnect lines in a CMOS process for high speed RF and microwave applications'20036,492,716'Seal ring structure for IC containing integrated digital/RF/analog circuits and functions'20026,472,253'Programmable semiconductor device structures and methods for making the same'20026,411,367'Modified optics for imaging of lens limited subresolution features'20026,399,432'Process to control poly silicon profiles in a dual doped poly silicon process'20026,387,720'Waveguide structures integrated with standard CMOS circuitry and methods for making the same'20026,387,797'Method for reducing the capacitance between interconnects by forming voids in dielectric material'20026,372,522'Use of optimized film stacks for increasing absorption for laser repair of fuse links'20026,355,969'Programmable integrated circuit structures and methods for making the same'20026,327,695'Automated design of on-chip capacitive structures for suppressing inductive noise'20016,323,113'Intelligent gate-level fill methods for reducing global pattern density effects'20016,313,466'Method for determining nitrogen concentration in a film of nitrided oxide material'20016,303,192'Process to improve adhesion of PECVD cap layers in integrated circuits'20016,297,557'Reliable aluminum interconnect via structures'20016,281,585'Air gap dielectric in self-aligned via structures'20016,277,708'Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same'20016,275,971'Methods and apparatus for design rule checking'20016,261,939'Pad metallization over active circuitry'20016,229,685'Thin capacitive structures and methods for making the same'20016,226,782'Apparatus for automated pillar layout'20016,221,759'Method for forming aligned vias under trenches in a dual damascene process'20016,214,734'Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection'20016,191,481'Electromigration impeding composite metallization lines and methods for making the same'20016,189,136'Design level optical proximity correction methods'20016,176,983'Methods of forming a semiconductor device'20016,162,586'Method for substantially preventing footings in chemically amplified deep ultra violet photoresist layers'20006,159,844'Fabrication of gate and diffusion contacts in self-aligned contact process'20006,156,626'Electromigration bonding process and system'20006,153,531'Method for preventing electrochemical erosion of interconnect structures'20006,143,642'Programmable semiconductor structures and methods for making the same'20006,140,221'Method for forming vias through porous dielectric material and devices formed thereby'20006,140,188'Semiconductor device having load device with trench isolation region and fabrication thereof'20006,133,111'Method of making photo alignment structure'20006,133,635'Process for making self-aligned conductive via structures'20006,129,613'Semiconductor manufacturing apparatus and method for measuring in-situ pressure across a wafer'20006,127,811'Micro-electromechanical system and voltage shifter, method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system'20006,093,658'Method for making reliable interconnect structures'20006,080,661'Methods for fabricating gate and diffusion contacts in self-aligned contact processes'20006,077,762'Method and apparatus for rapidly discharging plasma etched interconnect structures'20006,057,224'Methods for making semiconductor devices having air dielectric interconnect structures'20006,054,378'Method for encapsulating a metal via in damascene'20006,046,102'Moisture barrier gap fill structure and method for making the same'20006,034,434'Optimized underlayer structures for maintaining chemical mechanical polishing removal rates'20006,030,885'Hexagonal semiconductor die, semiconductor substrates, and methods of forming a semiconductor die'20006,028,013'Moisture repellant integrated circuit dielectric material combination'20006,020,616'Automated design of on-chip capacitive structures for suppressing inductive noise'20006,020,647'Composite metallization structures for improved post bonding reliability'20006,013,927'Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same'20006,013,536'Apparatus for automated pillar layout and method for implementing same'20006,010,939'Methods for making shallow trench capacitive structures'20005,985,749'Method of forming a via hole structure including CVD tungsten silicide barrier layer'19995,981,378'Reliable interconnect via structures and methods for making the same'19995,976,987'In-situ corner rounding during oxide etch for improved plug fill'19995,965,218'Process for manufacturing ultra-sharp atomic force microscope (AFM) and scanning tunneling microscope (STM) tips'19995,965,941'Use of dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing'19995,963,784'Methods of determining parameters of a semiconductor device and the width of an insulative spacer of a semiconductor device'19995,933,020'Parasitic resistance measuring device'19995,928,968'Semiconductor pressure transducer structures and methods for making the same'19995,916,016'Methods and apparatus for polishing wafers'19995,915,203'Method for producing deep submicron interconnect vias'19995,913,141'Reliable interconnect via structures and methods for making the same'19995,889,389'Micro-electromechanical voltage shifter'19995,882,998'Low power programmable fuse structures and methods for making the same'19995,882,997'Method for making devices having thin load structures'19995,880,519'Moisture barrier gap fill structure and method for making the same'19995,877,562'Photo alignment structure'19995,854,510'Low power programmable fuse structures'19985,834,356'Method of making high resistive structures in salicided process semiconductor devices'19985,798,559'Integrated circuit structure having an air dielectric and dielectric support pillars'19985,783,488'Optimized underlayer structures for maintaining chemical mechanical polishing removal rates'19985,764,563'Thin film load structure'19985,639,697'Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing'19975,618,757'Method for improving the manufacturability of the spin-on glass etchback process'19975,597,668'Patterned filled photo mask generation for integrated circuit manufacturing'19975,540,958'Method of making microscope probe tips'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2002Patents assigned to VLSI TECHNOLOGY INC (42)· patent assignee history
1996–2005Based in San Jose, CA, US· patent location history
2000–2003Patents assigned to PHILIPS ELECTRONICS NA (24)· patent assignee history
2000–2002Patents assigned to PHILIPS SEMICONDUCTORS INC (3)· patent assignee history
2001–2012Based in Fremont, CA, US· patent location history
2003–2005Patents assigned to KONINKL PHILIPS ELECTRONICS NV (6)· patent assignee history
2006–2012Patents assigned to BROADCOM CORP (7)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
VLSI TECHNOLOGY INC421996–2002
PHILIPS ELECTRONICS NA242000–2003
BROADCOM CORP72006–2012
KONINKL PHILIPS ELECTRONICS NV62003–2005
PHILIPS SEMICONDUCTORS INC32000–2002
Locations
LocationPatentsSpan
San Jose, California, US691996–2005
Fremont, California, US212001–2012