Inventor

Tuung Luoh

Inventor
Taipei, TW

Overview

35→
Patents
2005–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 35 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10DInorganic electric semiconductor devices12%
H01JElectric discharge tubes or discharge lamps7%
H01LSemiconductor devices7%
H10BElectronic memory devices7%
G01NInvestigating or analysing materials by determining their chemical or physical properties5%
G01RMeasuring electric variables4%
G11CStatic stores4%
G06FElectric digital data processing3%
PatentTitleYear
10,892,265Word line structure and method of manufacturing the same202110,497,652Semiconductor substrate and semiconductor device201910,388,664Integrated circuit device with layered trench conductors20199,869,712'Method and system for detecting defects of wafer by wafer sort'20189,589,086'Method for measuring and analyzing surface structure of chip or wafer'20179,244,112'Method for detecting an electrical defect of contact/via plugs'20169,116,108'Electron beam inspection optimization'20159,006,003'Method of detecting bitmap failure associated with physical coordinate'20158,828,861'Method for fabricating conductive lines of a semiconductor device'20148,669,184'Method for improving flatness of a layer deposited on polycrystalline layer'20148,653,592'Isolation structure, non-volatile memory having the same, and method of fabricating the same'20148,594,963'In-line inspection yield prediction system'20138,580,680'Metal silicide formation'20138,520,194'Method of forming a deposited material by utilizing a multi-step deposition/etch/deposition (D/E/D) process'20138,519,541'Semiconductor device having plural conductive layers disposed within dielectric layer'20138,383,515'Methodology for wordline short reduction'20138,329,480'Test pattern for detecting piping in a memory array'20128,184,288'Method of depositing a silicon-containing material by utilizing a multi-step fill-in process in a deposition machine'20128,085,390'Multivariate monitoring method for plasma process machine'20118,067,292'Isolation structure, non-volatile memory having the same, and method of fabricating the same'20118,034,691'HDP-CVD process, filling-in process utilizing HDP-CVD, and HDP-CVD system'20118,003,519'Systems and methods for back end of line processing of semiconductor circuits'20117,951,707'Etching method for semiconductor element'20117,938,972'Fabrication method of electronic device'20117,888,804'Method for forming self-aligned contacts and local interconnects simultaneously'20117,846,835'Contact barrier layer deposition process'20107,629,265'Cleaning method for use in semiconductor device fabrication'20097,625,819'Interconnection process'20097,517,780'Method for eliminating polycide voids through nitrogen implantation'20097,498,257'Methods for metal ARC layer formation'20097,382,054'Method for forming self-aligned contacts and local interconnects simultaneously'20087,335,610'Ultraviolet blocking layer'20087,148,105'Method for forming polysilicon floating gate'20067,045,419'Elimination of the fast-erase phenomena in flash memory'20066,962,861'Method of forming a polysilicon layer comprising microcrystalline grains'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2021Patents assigned to MACRONIX INT CO LTD (35)· patent assignee history
2005–2018Based in Hsinchu, TW· patent location history
2006–2021Based in Taipei, TW· patent location history
2011–2014Patents assigned to LUOH TUUNG (12)· patent assignee history
2011–2014Patents assigned to CHEN KUANG-CHAO (11)· patent assignee history
2011–2014Patents assigned to SU CHIN-TA (8)· patent assignee history
2011–2014Patents assigned to YANG TA-HUNG (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MACRONIX INT CO LTD352005–2021
LUOH TUUNGself122011–2014
CHEN KUANG-CHAO112011–2014
SU CHIN-TA82011–2014
YANG TA-HUNG62011–2014
Locations
LocationPatentsSpan
Taipei, TW182006–2021
Hsinchu, TW172005–2018