Inventor
Glen L. Miles
Inventor
Essex Junction, VT, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices42%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
C30BSingle-crystal growth8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
B64DEquipment for fitting in or to aircraft3%
C23CCoating metallic material3%
G01KMeasuring temperature3%
G06FElectric digital data processing3%
H02JElectric power networks3%
PatentTitleYear
11,121,773Split power-control electronics with fiber-optic multiplexing20218,136,084'Arranging through silicon vias in IC layout'20127,714,366'CMOS transistor with a polysilicon gate electrode having varying grain size'20106,893,948'Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size'20056,853,032'Structure and method for formation of a blocked silicide resistor'20056,670,263'Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size'20036,660,664'Structure and method for formation of a blocked silicide resistor'20036,509,265'Process for manufacturing a contact barrier'20036,348,419'Modification of the wet characteristics of deposited layers and in-line control'20026,250,803'Method for temperature measurement using dopant segregation into titanium silicide'20016,235,597'Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication'20016,187,679'Low temperature formation of low resistivity titanium silicide'20016,180,456'Triple polysilicon embedded NVRAM cell and method thereof'20016,180,521'Process for manufacturing a contact barrier'20016,069,040'Fabricating a floating gate with field enhancement feature self-aligned to a groove'20006,060,358'Damascene NVRAM cell and method of manufacture'20005,828,131'Low temperature formation of low resistivity titanium silicide'19985,510,295'Method for lowering the phase transformation temperature of a metal silicide'19964,983,544'Silicide bridge contact process'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2012Patents assigned to IBM (18)· patent assignee history
1991Based in South Burlington, VT, US· patent location history
1996–2010Based in Essex Junction, VT, US· patent location history
2002Patents assigned to INFINEON TECHNOLOGIES AG (1)· patent assignee history
2012Patents assigned to DEAN JR DONALD R (1)· patent assignee history
2012Patents assigned to LINDGREN PETER J (1)· patent assignee history
2012Based in Hopewell Junction, NY, US· patent location history
2021Patents assigned to HAMILTON SUNDSTRAND CORP (1)· patent assignee history
2021Based in Stillman Valley, IL, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 18 | 1991–2012 |
| DEAN JR DONALD R | 1 | 2012 |
| HAMILTON SUNDSTRAND CORP | 1 | 2021 |
| INFINEON TECHNOLOGIES AG | 1 | 2002 |
| LINDGREN PETER J | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 16 | 1996–2010 |
| Stillman Valley, Illinois, US | 1 | 2021 |
| Hopewell Junction, New York, US | 1 | 2012 |
| South Burlington, VT, US | 1 | 1991 |