Inventor
Juan-Carlos Calderon
Inventor
Fremont, CA, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Jprimary
H04JMultiplex communication35%
H04LTransmission of digital information, e.g. telegraphic communication31%
G06FElectric digital data processing10%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
H04BTransmission8%
H03MCoding6%
H04QSelecting2%
PatentTitleYear
9,787,431'Apparatus and method for forward error correction over a communication channel'20179,647,761'Flexible rate communication signalling'20179,461,764'Apparatus and method for communicating data over a communication channel'20169,438,376'Apparatus and method for forward error correction over a communication channel'20169,430,378'Differential delay compensation'20169,252,903'System and method for accounting for time that a packet spends in transit through a transparent clock'20169,110,794'Differential delay compensation'20158,862,797'Reducing delay and delay variation in a buffer in network communications'20148,494,363'Signal format conversion apparatus and methods'20138,488,631'Differential delay compensation'20138,392,788'Transport network system with transparent transport and method of operation thereof'20138,018,926'Differential delay compensation'20117,656,891'Method and apparatus enabling concurrent processing of contiguously and virtually concatenated payloads'20107,606,269'Method and apparatus for detecting and managing loss of alignment in a virtually concatenated group'20097,583,599'Transporting stream client signals via packet interface using GFP mapping'20097,564,777'Techniques for group alarm indication signal generation and clearing'20097,525,977'Control mechanism for mapping cells and packets'20097,508,830'Method and apparatus differential delay compensation processing of virtually concatenated data'20097,460,545'Enhanced SDRAM bandwidth usage and memory management for TDM traffic'20087,298,744'Method and apparatus for centralized processing of contiguously and virtually concatenated payloads'20077,295,564'Virtual output queue (VoQ) management method and apparatus'20077,154,853'Rate policing algorithm for packet flows'20067,065,628'Increasing memory access efficiency for packet applications'20067,061,867'Rate-based scheduling for packet applications'20066,944,728'Interleaving memory access'20056,892,284'Dynamic memory allocation for assigning partitions to a logical port from two groups of un-assigned partitions based on two threshold values'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2010Patents assigned to INTEL CORP (14)· patent assignee history
2005–2017Based in Fremont, CA, US· patent location history
2011–2016Patents assigned to CALDERON JUAN-CARLOS (6)· patent assignee history
2013–2016Patents assigned to CORTINA SYSTEMS INC (6)· patent assignee history
2013–2016Patents assigned to CAIA JEAN-MICHEL (4)· patent assignee history
2013–2016Patents assigned to MICRON TECHNOLOGY INC (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 14 | 2005–2010 |
| CALDERON JUAN-CARLOSself | 6 | 2011–2016 |
| CORTINA SYSTEMS INC | 6 | 2013–2016 |
| CAIA JEAN-MICHEL | 4 | 2013–2016 |
| MICRON TECHNOLOGY INC | 3 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 26 | 2005–2017 |