Inventor
EKMINI ANUJA DE SILVA
Inventor
US
Overview
Patents· 48 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H10DInorganic electric semiconductor devices9%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices7%
H10NElectric solid-state devices not otherwise provided for6%
H10BElectronic memory devices5%
B82YSpecific uses or applications of nanostructures4%
C07FAcyclic, carbocyclic or heterocyclic compounds containing elements other than carbon, hydrogen, halogen, oxygen, nitrogen, sulfur, selenium or tellurium1%
C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds1%
PatentTitleYear
12,363,913Fabrication of embedded memory devices utilizing a self assembled monolayer202512,310,100Dielectric reflow for boundary control202512,183,630Additive interconnect formation202412,125,790Airgap isolation for back-end-of-the-line semiconductor interconnect structure with top via202412,033,856Litho-litho-etch (LLE) multi color resist202412,020,949Subtractive patterning of interconnect structures202412,002,856Vertical field effect transistor with crosslink fin arrangement202411,990,342Metal cut patterning and etching to minimize interlayer dielectric layer loss202411,935,931Selective shrink for contact trench202411,923,246Via CD controllable top via structure202411,923,311Forming self-aligned multi-metal interconnects202411,916,143Vertical transport field-effect transistor with gate patterning202411,906,901Alternating copolymer chain scission photoresists202411,856,878High-density resistive random-access memory array with self-aligned bottom electrode contact202311,830,807Placing top vias at line ends by selective growth of via mask from line cut dielectric202311,810,828Transistor boundary protection using reversible crosslinking reflow202311,804,401Spacer-defined process for lithography-etch double patterning for interconnects202311,778,929Selective encapsulation for metal electrodes of embedded memory devices202311,756,961Staggered stacked vertical crystalline semiconducting channels202311,751,492Embedded memory pillar202311,744,083Fabrication of embedded memory devices utilizing a self assembled monolayer202311,699,592Inverse tone pillar printing method using organic planarizing layer pillars202311,688,636Spin on scaffold film for forming topvia202311,682,558Fabrication of back-end-of-line interconnects202311,621,326Vertical field effect transistor with crosslink fin arrangement202311,562,908Dielectric structure to prevent hard mask erosion202311,561,481Using E0 exposures for track/cluster monitoring202311,543,751Organic photoresist adhesion to metal oxide hardmasks202311,521,894Partial wrap around top contact202211,515,431Enabling residue free gap fill between nanosheets202211,508,823Low capacitance low RC wrap-around-contact202211,500,290Adhesion promoters202211,501,969Direct extreme ultraviolet lithography on hard mask with reverse tone202211,500,293Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer202211,373,880Creating different width lines and spaces in a metal layer202211,355,442Forming self-aligned multi-metal interconnects202211,307,496Metal brush layer for EUV patterning202211,300,881Line break repairing layer for extreme ultraviolet patterning stacks202211,302,573Semiconductor structure with fully aligned vias202211,251,182Staggered stacked vertical crystalline semiconducting channels202211,239,077Litho-etch-litho-etch with self-aligned blocks202211,226,561Self-priming resist for generic inorganic hardmasks202211,205,678Embedded MRAM device with top via202111,195,995Back-end-of-line compatible processing for forming an array of pillars202111,194,254Lithography process delay characterization and effective dose compensation202111,189,561Placing top vias at line ends by selective growth of via mask from line cut dielectric202111,177,130Patterning material film stack with metal-containing top coat for enhanced sensitivity in extreme ultraviolet (EUV) lithography202111,164,772Spacer-defined process for lithography-etch double patterning for interconnects2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to IBM (48)· patent assignee history
2021–2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 48 | 2021–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 48 | 2021–2025 |