Inventor
Feng Lin
Inventor
Boise, ID, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores39%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses39%
G01RMeasuring electric variables6%
H03KPulse technique6%
G06FElectric digital data processing3%
H03DDemodulation or transference of modulation from one carrier to another3%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
8,218,708'Phase splitter using digital delay locked loops'20128,212,595'System and method to improve the efficiency of synchronous mirror delays and delay locked loops'20127,982,519'Centralizing the lock point of a synchronous circuit'20117,881,149'Write latency tracking using a delay lock loop in a synchronous DRAM'20117,873,131'Phase splitter using digital delay locked loops'20117,830,194'Centralizing the lock point of a synchronous circuit'20107,593,286'Write latency tracking using a delay lock loop in a synchronous DRAM'20097,480,203'Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM'20097,355,922'Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM'20087,355,920'Write latency tracking using a delay lock loop in a synchronous DRAM'20087,336,111'Fast-locking digital phase locked loop'20087,332,946'Power supply voltage detection circuitry and methods for use of the same'20087,221,201'Fast-locking digital phase locked loop'20077,161,391'Skew tolerant high-speed digital phase detector'20077,148,742'Power supply voltage detection circuitry and methods for use of the same'20067,065,001'Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM'20066,839,860'Capture clock generator using master and slave delay locked loops'20056,836,166'Method and system for delay control in synchronization circuits'20046,687,185'Method and apparatus for setting and compensating read latency in a high speed DRAM'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2011Patents assigned to MICRON TECHNOLOGY INC (14)· patent assignee history
2004–2012Based in Boise, ID, US· patent location history
2010–2012Patents assigned to ROUND ROCK RES LLC (5)· patent assignee history
2012Patents assigned to LIN FENG (2)· patent assignee history
2012Patents assigned to BAKER R JACOB (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 14 | 2004–2011 |
| ROUND ROCK RES LLC | 5 | 2010–2012 |
| LIN FENGself | 2 | 2012 |
| BAKER R JACOB | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 19 | 2004–2012 |