Inventor

BISWAJEET GUHA

Inventor

US

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 102 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices30%

H01LSemiconductor devices25%

B82YSpecific uses or applications of nanostructures22%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%

H10BElectronic memory devices2%

G11CStatic stores1%

H03KPulse technique1%

G06FElectric digital data processing0%

PatentTitleYear

12,575,151Gate-all-around integrated circuit structures having doped subfin2026 12,568,643Nanowire transistors and methods of fabrication2026 12,563,737Memory device fabrication through wafer bonding2026 12,507,464—2025 12,507,475—2025 12,484,272Source or drain structures with relatively high germanium content2025 12,484,266Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers2025 12,464,815Fin cut in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication2025 12,464,730Method of forming capacitors through wafer bonding2025 12,453,115Nanowire transistor structure and method of shaping2025 12,445,134Diode connected non-linear input capacitors based majority gate2025 12,426,316Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material2025 12,419,091Source electrode and drain electrode protection for nanowire transistors2025 12,412,611Time decoupled write operations for non-linear polar material based memory2025 12,402,349Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact2025 12,382,706Self-aligned gate endcap (SAGE) architectures with gate-all-around devices2025 12,369,392Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates2025 12,369,393Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach2025 12,364,002Integrated circuit structures having metal gates with tapered plugs2025 12,349,394Dielectric isolation layer between a nanowire transistor and a substrate2025 12,342,612Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions2025 12,336,278Gate-all-around integrated circuit structures having high mobility2025 12,328,947Substrate-less silicon controlled rectifier (SCR) integrated circuit structures2025 12,328,905Cavity spacer for nanowire transistors2025 12,328,920Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy2025 12,317,590Substrate-free integrated circuit structures2025 12,302,632Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process2025 12,294,006Gate-all-around integrated circuit structures having insulator substrate2025 12,288,808High aspect ratio source or drain structures with abrupt dopant profile2025 12,288,789Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact2025 12,272,737Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact2025 12,230,717Integrated circuit structures having partitioned source or drain contact structures2025 12,230,721Gate-all-around integrated circuit structures having asymmetric source and drain contact structures2025 12,224,350Self-aligned gate endcap (SAGE) architectures with gate-all-around devices2025 12,211,925Gate-all-around integrated circuit structures having oxide sub-fins2025 12,206,027Gate-all-around integrated circuit structures having nanowires with tight vertical spacing2025 12,199,143Gate-all-around integrated circuit structures having removed substrate2025 12,176,429Wrap-around contact structures for semiconductor nanowires and nanoribbons2024 12,166,031Substrate-less electrostatic discharge (ESD) integrated circuit structures2024 12,159,901Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs2024 12,068,314Fabrication of gate-all-around integrated circuit structures having adjacent island structures2024 12,057,491Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates2024 12,014,959Integrated nanowire and nanoribbon patterning in transistor manufacture2024 12,002,810Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach2024 11,990,472Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates2024 11,984,449Channel structures with sub-fin dopant diffusion blocking layers2024 11,929,396Cavity spacer for nanowire transistors2024 11,908,856Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact2024 11,901,458Dielectric isolation layer between a nanowire transistor and a substrate2024 11,894,368Gate-all-around integrated circuit structures fabricated using alternate etch selective material2024 11,869,987Gate-all-around integrated circuit structures including varactors2024 11,869,973Nanowire transistor structure and method of shaping2024 11,869,891Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process2024 11,862,635Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions2024 11,855,223Self-aligned gate endcap (SAGE) architectures with gate-all-around devices2023 11,837,641Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact2023 11,824,116Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact2023 11,824,107Wrap-around contact structures for semiconductor nanowires and nanoribbons2023 11,804,523High aspect ratio source or drain structures with abrupt dopant profile2023 11,799,009Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact2023 11,799,037Gate-all-around integrated circuit structures having asymmetric source and drain contact structures2023 11,769,836Gate-all-around integrated circuit structures having nanowires with tight vertical spacing2023 11,757,037Epitaxial oxide plug for strained transistors2023 11,749,733FIN shaping using templates and integrated circuit structures resulting therefrom2023 11,742,410Gate-all-around integrated circuit structures having oxide sub-fins2023 11,715,775Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures2023 11,715,787Self-aligned nanowire2023 11,705,518Isolation schemes for gate-all-around transistor devices2023 11,676,965Strained tunable nanowire structures and process2023 11,621,354Integrated circuit structures having partitioned source or drain contact structures2023 11,594,637Gate-all-around integrated circuit structures having fin stack isolation2023 11,588,052Sub-Fin isolation schemes for gate-all-around transistor devices2023 11,581,315Self-aligned gate edge trigate and finFET devices2023 11,569,370DEPOP using cyclic selective spacer etch2023 11,538,937Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material2022 11,538,806Gate-all-around integrated circuit structures having high mobility2022 11,527,640Wrap-around contact structures for semiconductor nanowires and nanoribbons2022 11,527,612Gate-all-around integrated circuit structures having vertically discrete source or drain structures2022 11,522,048Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs2022 11,521,968Channel structures with sub-fin dopant diffusion blocking layers2022 11,495,672Increased transistor source/drain contact area using sacrificial source/drain layer2022 11,469,299Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers2022 11,456,357Self-aligned gate edge architecture with alternate channel material2022 11,450,739Germanium-rich nanowire transistor with relaxed buffer layer2022 11,450,738Source/drain regions in integrated circuit structures2022 11,430,868Buried etch-stop layer to help control transistor source/drain depth2022 11,417,781Gate-all-around integrated circuit structures including varactors2022 11,411,096Source electrode and drain electrode protection for nanowire transistors2022 11,404,578Dielectric isolation layer between a nanowire transistor and a substrate2022 11,398,474Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions2022 11,374,100Source or drain structures with contact etch stop layer2022 11,367,796Gate-all-around integrated circuit structures having asymmetric source and drain contact structures2022 11,355,608Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures2022 11,342,411Cavity spacer for nanowire transistors2022 11,335,807Isolation schemes for gate-all-around transistor devices2022 11,302,790Fin shaping using templates and integrated circuit structures resulting therefrom2022 11,276,691Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths2022 11,251,302Epitaxial oxide plug for strained transistors2022 11,233,152Self-aligned gate endcap (SAGE) architectures with gate-all-around devices2022 11,205,715Self-aligned nanowire2021 11,164,790Integrated nanowire and nanoribbon patterning in transistor manufacture2021 11,152,461Semiconductor layer between source/drain regions and gate spacers2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to INTEL CORP (98)· patent assignee history

2021–2026Based in US· patent location history

2025–2026Patents assigned to KEPLER COMPUTING INC (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	98	2021–2026
KEPLER COMPUTING INC	4	2025–2026

Locations

Location	Patents	Span
US	102	2021–2026