Inventor

Ruqiang Bao

Inventor

Niskayuna, NY, US

Overview

2016–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 134 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices34%

H10DInorganic electric semiconductor devices33%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%

B82YSpecific uses or applications of nanostructures5%

H10BElectronic memory devices4%

H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner0%

H03JTuning resonant circuits0%

H05KPrinted circuits0%

H10NElectric solid-state devices not otherwise provided for0%

PatentTitleYear

11,107,814Vertical fin field effect transistor devices with a replacement metal gate2021 11,094,801Oxide isolated fin-type field-effect transistors2021 11,075,281Additive core subtractive liner for metal cut etch processes2021 11,011,517Semiconductor structure including first FinFET devices for low power applications and second FinFET devices for high power applications2021 11,004,850Vertical fin field effect transistor devices with a replacement metal gate2021 10,985,075Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages2021 10,971,399Oxygen-free replacement liner for improved transistor performance2021 10,971,626Interface charge reduction for SiGe surface2021 10,957,696Self-aligned metal gate with poly silicide for vertical transport field-effect transistors2021 10,957,646Hybrid BEOL metallization utilizing selective reflection mask2021 10,943,989Gate to source/drain leakage reduction in nanosheet transistors via inner spacer optimization2021 10,937,648Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS2021 10,930,734Nanosheet FET bottom isolation2021 10,903,418Low resistance electrode for high aspect ratio confined PCM cell in BEOL2021 10,903,124Transistor structure with n/p boundary buffer2021 10,892,339Gate first technique in vertical transport FET using doped silicon gates with silicide2021 10,832,975Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement2020 10,833,146Horizontal-trench capacitor2020 10,804,368Semiconductor device having two-part spacer2020 10,797,163Leakage control for gate-all-around field-effect transistor devices2020 10,790,271Perpendicular stacked field-effect transistor device2020 10,790,199Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering2020 10,777,469Self-aligned top spacers for vertical FETs with in situ solid state doping2020 10,777,659Self-aligned bottom source/drain epitaxial growth in vertical field effect transistors2020 10,756,194Shared metal gate stack with tunable work function2020 10,749,012Formation of self-aligned bottom spacer for vertical transistors2020 10,741,663Encapsulation layer for vertical transport field-effect transistor gate stack2020 10,741,401Self-aligned semiconductor gate cut2020 10,692,778Gate-all-around FETs having uniform threshold voltage2020 10,692,873Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions2020 10,692,990Gate cut in RMG2020 10,679,993Vertical fin field effect transistor devices with a replacement metal gate2020 10,680,083Oxide isolated fin-type field-effect transistors2020 10,679,901Differing device characteristics on a single wafer by selective etch2020 10,672,905Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts2020 10,672,910Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)2020 10,672,670Replacement metal gate process for vertical transport field-effect transistors with multiple threshold voltages2020 10,658,521Enabling residue free gap fill between nanosheets2020 10,658,299Replacement metal gate processes for vertical transport field-effect transistor2020 10,658,973Reconfigurable allocation of VNCAP inter-layer vias for co-tuning of L and C in LC tank2020 10,644,129Gate cut in RMG2020 10,629,495Low undercut N-P work function metal patterning in nanosheet replacement metal gate process2020 10,622,489Vertical tunnel FET with self-aligned heterojunction2020 10,615,083Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device2020 10,615,082VFET metal gate patterning for vertical transport field effect transistor2020 10,608,121FinFET transistor gate and epitaxy formation2020 10,607,990Fabrication of field effect transistors with different threshold voltages through modified channel interfaces2020 10,600,884Additive core subtractive liner for metal cut etch processes2020 10,586,767Hybrid BEOL metallization utilizing selective reflection mask2020 10,586,854Gate-all-around field effect transistor having multiple threshold voltages2020 10,580,881Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices2020 10,553,498Integrated circuit with replacement gate stacks and method of forming same2020 10,553,700Gate cut in RMG2020 10,546,787Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device2020 10,535,517Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS2020 10,529,815Conformal replacement gate electrode for short channel devices2020 10,529,628Semiconductor device and method of forming the semiconductor device2020 10,490,559Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions2019 10,468,412Formation of a semiconductor device with selective nitride grown on conductor2019 10,439,043Formation of self-aligned bottom spacer for vertical transistors2019 10,418,288Techniques for forming different gate length vertical transistors with dual gate oxide2019 10,395,989Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETs2019 10,395,988Vertical FET transistor with reduced source/drain contact resistance2019 10,381,479Interface charge reduction for SiGe surface2019 10,373,912Replacement metal gate processes for vertical transport field-effect transistor2019 10,361,132Structures with thinned dielectric material2019 10,361,130Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering2019 10,354,999Structure and method to suppress work function effect by patterning boundary proximity in replacement metal gate2019 10,340,340Multiple-threshold nanosheet transistors2019 10,332,883Integrated metal gate CMOS devices2019 10,325,815Vertical transport fin field effect transistors having different channel lengths2019 10,312,147Multi-layer work function metal gates with similar gate thickness to achieve multi-VT for VFETs2019 10,312,157Field effect transistor stack with tunable work function2019 10,312,237Vertical transport transistors with equal gate stack thicknesses2019 10,297,671Uniform threshold voltage for nanosheet devices2019 10,297,598Formation of full metal gate to suppress interficial layer growth2019 10,283,620Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices2019 10,276,687Formation of self-aligned bottom spacer for vertical transistors2019 10,276,452Low undercut N-P work function metal patterning in nanosheet replacement metal gate process2019 10,263,098Threshold voltage modulation through channel length adjustment2019 10,256,159Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device2019 10,249,543Field effect transistor stack with tunable work function2019 10,242,919Vertical transport fin field effect transistors having different channel lengths2019 10,243,055Shared metal gate stack with tunable work function2019 10,236,219VFET metal gate patterning for vertical transport field effect transistor2019 10,224,419Threshold voltage modulation through channel length adjustment2019 10,204,828Enabling low resistance gates and contacts integrated with bilayer dielectrics2019 10,170,640FinFET transistor gate and epitaxy formation2019 10,170,593Threshold voltage modulation through channel length adjustment2019 10,170,477Forming MOSFET structures with work function modification2019 10,157,923Vertical transport transistors with equal gate stack thicknesses2018 10,147,725Forming MOSFET structures with work function modification2018 10,134,642Semiconductor device and method of forming the semiconductor device2018 10,128,372Bottom contact resistance reduction on VFET2018 10,128,347Gate-all-around field effect transistor having multiple threshold voltages2018 10,109,722Etch-resistant spacer formation on gate structure2018 10,103,147Vertical transport transistors with equal gate stack thicknesses2018 10,084,055Uniform threshold voltage for nanosheet devices2018 10,084,082Bottom contact resistance reduction on VFET2018 10,079,182Field effect transistor gate stack2018 10,074,574Integrated circuit with replacement gate stacks and method of forming same2018 10,068,805Self-aligned spacer for cut-last transistor fabrication2018 10,032,856Nanosheet capacitor2018 10,020,255Integration of super via structure in BEOL2018 10,020,254Integration of super via structure in BEOL2018 10,020,378Self-aligned spacer for cut-last transistor fabrication2018 10,008,417Vertical transport fin field effect transistors having different channel lengths2018 10,002,937Shared metal gate stack with tunable work function2018 10,002,791Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS2018 9,997,518Low resistive electrode for an extendable high-k metal gate stack2018 9,997,519Dual channel structures with multiple threshold voltages2018 9,960,161Low resistive electrode for an extendable high-k metal gate stack2018 9,960,272Bottom contact resistance reduction on VFET2018 9,941,282Integrated metal gate CMOS devices2018 9,922,984'Threshold voltage modulation through channel length adjustment'2018 9,922,884'Integrated circuit with replacement gate stacks and method of forming same'2018 9,922,983'Threshold voltage modulation through channel length adjustment'2018 9,917,210'FinFET transistor gate and epitaxy formation'2018 9,905,476'Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs'2018 9,899,264'Integrated metal gate CMOS devices'2018 9,859,169'Field effect transistor stack with tunable work function'2018 9,818,746'Structure and method to suppress work function effect by patterning boundary proximity in replacement metal gate'2017 9,799,656'Semiconductor device having a gate stack with tunable work function'2017 9,768,171'Method to form dual tin layers as pFET work metal stack'2017 9,704,758'Forming a semiconductor structure for reduced negative bias temperature instability'2017 9,704,754'Self-aligned spacer for cut-last transistor fabrication'2017 9,691,655'Etch stop in a dep-etch-dep process'2017 9,589,806'Integrated circuit with replacement gate stacks and method of forming same'2017 9,583,400'Gate stack with tunable work function'2017 9,576,958'Forming a semiconductor structure for reduced negative bias temperature instability'2017 9,559,016'Semiconductor device having a gate stack with tunable work function'2017 9,553,092'Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs'2017 9,502,307'Forming a semiconductor structure for reduced negative bias temperature instability'2016 9,343,372'Metal stack for reduced gate resistance'2016

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2016–2021Patents assigned to IBM (128)· patent assignee history

2016–2019Patents assigned to GLOBALFOUNDRIES INC (6)· patent assignee history

2016–2021Based in Wappingers Falls, NY, US· patent location history

2017–2021Based in Niskayuna, NY, US· patent location history

2018Based in Nisakayuna, NY, US· patent location history

2020Patents assigned to ELPIS TECH INC (1)· patent assignee history

2020Patents assigned to ULVAC INC (1)· patent assignee history

2020Based in Nishayuna, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	128	2016–2021
GLOBALFOUNDRIES INC	6	2016–2019
ELPIS TECH INC	1	2020
ULVAC INC	1	2020

Locations

Location	Patents	Span
Niskayuna, New York, US	93	2017–2021
Wappingers Falls, New York, US	39	2016–2021
Nishayuna, New York, US	1	2020
Nisakayuna, New York, US	1	2018