Inventor
An-Chun Tu
Inventor
Taipei, TW
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H10DInorganic electric semiconductor devices15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H01LSemiconductor devices12%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation12%
G01RMeasuring electric variables7%
C23CCoating metallic material5%
F28CHeat-exchange apparatus, not provided for in another subclass, in which the heat-exchange media come into direct contact without chemical interaction2%
F28DHeat-exchange apparatus, not provided for in another subclass, in which the heat-exchange media do not come into direct contact2%
F28FDetails of heat-exchange and heat-transfer apparatus, of general application2%
PatentTitleYear
9,377,503'Semiconductor test structures'20169,330,901'Nitrogen-containing oxide film and method of forming the same'20169,257,326'Method of making backside illuminated image sensors'20169,250,286'Semiconductor test structures'20168,946,847'Backside illuminated image sensors and method of making the same'20158,704,224'Semiconductor test structures'20148,674,469'Isolation structure for backside illuminated image sensor'20148,614,131'Self-aligned static random access memory (SRAM) on metal gate'20138,586,404'Method for reducing contact resistance of CMOS image sensor'20138,352,062'Advanced process control for gate profile control'20138,247,262'Method for reducing contact resistance of CMOS image sensor'20127,119,017'Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios'20066,849,546'Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios'20056,828,246'Gas delivering device'20046,309,957'Method of low-K/copper dual damascene'20016,030,456'Installation to supply gas'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2016Based in Taipei, TW· patent location history
2005–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (13)· patent assignee history
2012–2016Patents assigned to HUANG CHEN-MING (7)· patent assignee history
2012–2016Patents assigned to TU AN-CHUN (7)· patent assignee history
2012–2016Patents assigned to WU CHIH-JEN (6)· patent assignee history
2012–2014Patents assigned to HUANG KUAN-CHIEH (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 13 | 2005–2016 |
| HUANG CHEN-MING | 7 | 2012–2016 |
| TU AN-CHUNself | 7 | 2012–2016 |
| WU CHIH-JEN | 6 | 2012–2016 |
| HUANG KUAN-CHIEH | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 16 | 2000–2016 |